Sunday,
May 22 |
 |
|
08:00-09:00 |
Tutorials Registration
at Tallinn University of Technology |
|
|
09:00-12:00 |
TTEP Tutorials at
Tallinn University of Technology |
| |
Tutorial 1: System-on-Chip: Embedded
Test in Practice
Y. ZORIAN (Virage Logic USA) |
| |
Tutorial 2: Design-for-Test of Analog
and Mixed-Signal Integrated Circuits
J. L.HUERTAS (IMSE-CNM Spain) |
|
|
12:00-13:00 |
Lunch |
|
|
13:00-16:00 |
TTEP Tutorials at
Tallinn University of Technology |
| |
Tutorial 1: System-on-Chip: Embedded
Test in Practice
Y. ZORIAN (Virage Logic USA) |
| |
Tutorial 2: Design-for-Test of Analog
and Mixed-Signal Integrated Circuits
J. L. HUERTAS (IMSE-CNM Spain) |
|
|
16:00-18:00 |
Symposium Registration |
|
|
19:00- ... |
Reception at the Historic
Tallinn Town Hall |
|
|
Monday,
May 23 |
|
|
07:30-08:30 |
Symposium Registration |
|
|
08:30-10:00 |
Plenary Session |
Room Alfa |
Opening |
Welcome
R. UBAR (Tallinn University of Technology Estonia)
P. PRINETTO (Politecnico di Torino Italy) |
| |
Symposium Program
M. RENOVELL (LIRMM France) |
Keynotes |
State as Information System - Can
Policymakers Learn from Error Signals?
R. MALMSTEIN (Government Counsellor Estonia) |
| |
Test and Reliability in Automotive
Microelectronics
P. van STAA (Robert Bosch GmbH Germany) |
|
Defects and New Failure Mechanisms:
"To Test or not to Test"
J. FIGUERAS (Universitat Politenica de Catalunya - Spain) |
Organization |
Organizational Issues
J. RAIK (Tallinn University of Technology Estonia) |
|
|
10:00-11:00 |
PhD Forum |
|
| |
On
the High-Level Test Patterns Generation Problem
C. MARCONCINI (University of Verona - Italy) |
| |
The Implementation of a Dong's Code Protected
Multiplier
M. MARSHALL (University of Newcastle Upon Tyne UK) |
| |
System Behavior Analysis of Smart Cards
Based on High Level Fault Injection
K. ROTHBART, R. WEISS (Graz University of Technology Austria) |
|
|
10:00-11:00 |
Poster Session 1 |
|
| |
Fault Detection for the Elliptic Filter
L. MIRONOVSKY, X. PETROVA (St. Petersburg State University of Airspace
Instrumentation Russia) |
| |
Programmable RF Attenuator for On-Chip
Loopback Test
T. KANTASUWAN, R. RAMZAN, J. DABROWSKI (Linköping University Sweden) |
| |
Selection of Diagnosis Variables
for Single Fault Diagnosis in Linear Circuits
J. A. SOARES AUGUSTO (University of Lisbon Portugal) |
| |
Transient Functional Test of Analogue
Circuits
S. MOSIN (Vladimir State University Russia) |
| |
On the Application of the Oscillation-based
Test in High-order Ladder Filters
G. PERETTI, E. ROMERO (Universidad Tecnológica Nacional Argentine),
G.HUERTAS, D. VAZQUEZ, J. L HUERTAS (IMSE-CNM Spain) |
| |
Efficient Analog Fault Simulation
in AC Circuits
T. VEIGA, C. B. ALMEIDA, J. S. AUGUSTO (University of Lisboa Portugal) |
| |
A System for Determining the Impact of
Mechanical Stress on the Reliability of MEMS
M. DOELLE, S. SPINNER, P. RUTHER,
I. POLIAN, O. PAUL, B. BECKER (Albert-Ludwigs-University of Freiburg Germany) |
| 11:00-12:30 |
Session 2 |
| 11:00-12:30 |
Formal Session 2.a: SOC Testing |
Room Alfa |
| |
Moderators:
T. W. WILLIAMS (Synopsys USA), K. CHAKRABARTY (Duke University USA) |
| |
Energy Minimization
for Hybrid BIST in a System-on-Chip Test Environment
G. JERVAN (Linköping University - Sweden), R. J. UBAR, T. SHCHENOVA
(Tallinn University of Technology - Estonia), Z. PENG (Linköping University
- Sweden) |
| |
Test Scheduling for
Modular SOCs in an Abort-on-Fail Environment
U. INGELSSON (Linköping University - Sweden), S. GOEL (Philips
Research The Netherlands), E. LARSSON (Linköping University Sweden),
E. J. MARINISSEN (Philips Research Laboratories The Netherlands) |
| |
A New SoC Test Architecture
with RF/Wireless Connectivity
D. ZHAO (University of Louisiana at Lafayette - USA), S. UPADHYAYA (State
University of New York at Buffalo - USA), M. MARGALA (University of Rochester
- USA) |
11:00-12:30 |
Formal Session 2.b: Advances
in Fault and Defect Model |
Room Omega |
| |
Moderators:
A. SINGH (Auburn University USA) , R. AITKEN (Artisan Components USA) |
| |
An Unified Fault
Model and Test Generation Procedure for Interconnect Opens and Bridges
S. REDDY (University of Iowa USA), G. CHEN, J. RAJSKI (Mentor Graphics
USA), I. POMERANZ (Purdue University USA), P. ENGELKE, B. BECKER (University
of Freiburg Germany) |
| |
Defective Behaviours
of Resistive Opens in Interconnect Lines
D. ARUMI DELGADO, R. RODRÍGUEZ-MONTAÑÉS, J. FIGUERAS
(Universitat Politenica de Catalunya - Spain) |
| |
Testing of Resistive
Opens in CMOS Latches and Flip-flops
A. ZENTENO, V. CHAMPAC, J.L. GARCIA (National Institute for Astrophysics,
Optics and Electronics - Mexico) |
|
|
12:30-14:00 |
Lunch |
|
|
| 14:00-15:30 |
Session 3 |
| 14:00-15:30 |
Formal Session 3.a: Advanced
Test Generation Issues |
Room Alfa |
| |
Moderators: S.
HELLEBRAND (University of Paderborn Germany), I. POLIAN (Albert-Ludwigs-University
of Freiburg Germany) |
| |
Using Dummy Bridging
Faults to Define a Reduced Set of Target Faults
I. POMERANZ (Purdue University - USA), S. REDDY (University of Iowa
- USA) |
| |
Acceleration of Transition
Test Generation for Acyclic Sequential Circuits Utilizing Constrained Combinational
Stuck-at Test Generation
T. IWAGAKI, S. OHTAKE, H. FUJIWARA (Nara Institute of Science and Technology
- Japan) |
| |
Path-Oriented Transition
Fault Test Generation Considering Operating Conditions
B. SESHADRI (Purdue University - USA), I. POMERANZ (Purdue University
- USA), S. REDDY (University of Iowa - USA), S. KUNDU (University of Massachusetts
- USA) |
| 14:00-15:30 |
Formal Session 3.b: On-line
and BIST Techniques for MEMS |
Room Omega |
| |
Moderators: P.
TEIXEIRA (IST/INESC Portugal), J. TYSZER (Poznan University of Technology
Poland) |
| |
Towards On-Line
Testing Of MEMS Using Electro-Thermal Excitation
F. AZAIS, F. MAILLY, N. DUMAS, L. LATORRE, P. NOUET (LIRMM - CNRS / University
Montpellier 2 France) |
| |
Evaluation of Impulse
Response-Based BIST Techniques for MEMS in the Presence of Weak Nonlinearities
A. DHAYNI, S. MIR, L. RUFER (RMS Group - TIMA Laboratory INPG France) |
| |
Bias Superposition
On-line Testing of Sensors and Circuits
C. JEFFREY, Z. XU, A. RICHARDSON (Lancaster University - UK) |
|
|
| 15:30-16:30 |
Poster Session 2 |
|
| |
A Family of Logical Fault Models for Reversible
Circuits
I. POLIAN (Albert-Ludwigs-University of Freiburg Germany), J. HAYES
(University of Michigan USA), T. FIEHN, B. BECKER (Albert-Ludwigs-University
of Freiburg Germany) |
| |
Is Divergence at Fault Site a Necessary
Condition for Fault Detection?
S. KUNDU (University of Massachusetts USA) |
| |
PASSAT: Efficient SAT-based Test Pattern
Generation for Industrial Circuits
J. SHI, G. FEY, R. DRECHSLER (University of Bremen Germany), A. GLOWATZ,
F. HAPKE, J. SCHLÖFFEL (Philips Semiconductors GmbH Germany) |
| |
On the Extraction of a Minimum Cube to
Justify Signal Line Values
K. MIYASE, S. NAGAYAMA, S. KAJIHARA, X. WEN (Kyushu Institute of Technology
Japan), S. REDDY (University of Iowa USA) |
| |
Controller-Aware Hierarchical Test Generation
and Testability Analysis
M. HOSSEINABADY, P. LOTFI-KAMRAN, Z. NAVABI (University of Tehran
Iran) |
| |
High-performance Deductive Fault Simulation
Method
V. HAHANOV, I. HAHANOVA, V. OBRIZAN (Kharkiv National University of
Radioelectronics Ukraine) |
| |
An Efficient RTL Observability Evaluation
and Vector Generation Method
W. LU, T. LV, X. TAO YANG, X. WEI LI (Institute of Computing Technoloty,
CAS China) |
| |
Theoretical Fundamentals of Functional
Verification Based on Random Testbenches
I. UGARTE, P. SANCHEZ (University of Cantabria Spain) |
| |
A CLB Architecture for Online Correction
of SEU-based Errors in LUTs of SRAM-based FPGAs
E. SYAM SUNDAR REDDY, V. CHANDRASEKHAR, M. SASHIKANTH, V. KAMAKOTI (Indian
Institute of Technology, Madras India), N. VIJAYKRISHNAN (Pennsylvania
State University USA) |
| |
Efficient Methodology for Detection and
Correction of SEU-based Interconnect Errors in FPGAs using Partial Reconfiguration
E. SYAM SUNDAR REDDY, V. CHANDRASEKHAR, M. SASHIKANTH, V. KAMAKOTI (Indian
Institute of Technology, Madras India), N. VIJAYKRISHNAN (Pennsylvania
State University USA) |
|
|
| 16:30-18:00 |
Session 4 |
| 16:30-18:00 |
Formal Session 4.a: Low Cost
Testing for Advanced Analog Circuits |
Room Alfa |
| |
Moderators: J.L.
HUERTAS (Universidad De Sevilla Spain), G. GRONTHOUD (Phlips Research
The Netherlands) |
| |
Evaluation of Signature-Based
Testing of RF/Analog Circuits
A. C ZJAJO, J. PINEDA DE GYVEZ (Philips Research The Netherlands) |
| |
Accurate Measurement
of Multi-Tone Power Ratio (MTPR) of ADSL Devices using Low Cost Testers
G. SRINIVASAN (Georgia Institute of Technology - USA), S. CHERUBAL,
P. VARIYAM, M. TEKLU, C.-P. WANG, D. GUIDRY (Texas Instruments - USA), A.
CHATTERJEE (Georgia Institute of Technology - USA) |
| 16:30-18:00 |
Informal Session 4.b: Effective
Test Generation and Optimization |
Room Omega |
| |
Moderators:
A. CHATTERJEE (Georgia Institute of Technology USA), M. LUBASZEWSKI (Federal
University of Rio Grande do Sul Brazil) |
| |
An Advanced ATPG flow for complex SoC
design with PLL based scan test
V. VORISEK, H. LANG, (Freescale Semiconductor Germany) |
| |
Single and Multi-Bit Sigma-Delta Based
Analogue Signal Generation
T. O'SHEA, I. GROUT (University of Limerick - Ireland) |
| |
Test Process Efficiency Analysis with
Basic Quality Data
J. ANTILA (Nokia Networks Finland), M. MOILANEN (University of Oulu
Finland) |
|
|
19:00-20:30 |
Dinner |
|
|
20:30-22:00 |
Evening Panel 1a:
Nanoscale Technology - Is There A Change Of Paradigms In Testing ? |
Room Omega |
| |
We
expect higher density, higher functionality and even higher speed from
nanoscale technology, but it is paid by less reliability of the components
and larger variations of the devices. Robust designs and hardware-based
fault-tolerance seem to be the way out followed by the design community,
but what is the way test has to go?
|
| |
Moderator: R. AITKEN
(Artisan Components USA)
Organizer: H.-J. WUNDERLICH (University
of Stuttgart Germany) |
| |
Panelists:
B. BECKER (Albert-Ludwigs-University of Freiburg Germany)
A. CHATTERJEE (Georgia Institute of Technology USA)
J. FIGUERAS (Universitat Politenica de Catalunya Spain)
C. HAWKINS (University of New Mexico USA)
L. HUISMAN (IBM USA) |
20:30-22:00 |
Evening Panel 1b:
Microelectronics And Test in New Europe : Challenges and Opportunities in
Research and Industry |
Room Alfa |
| |
For
nearly 15 years, the international research community has bee united
again, but still the research conditions a rather diverse all over Europe.
This panel will discuss the new situations in the various countries,
in industry and academia. It targets a better mutual understanding and
a basis for improved collaboration within the European Union and across
the borders.
|
| |
Moderator: E.J.
MARINISSEN (Philips Research The Netherlands)Organizers: H.-J. WUNDERLICH
(University of Stuttgart Germany), R. UBAR (Tallinn University of Technology
Estonia) |
| |
Panelists:
V. HAHANOV (Kharkov National University of Radioelectronics Ukraine)
M. KARAVAI (Institute of Control Sciences Russia)
O. NOVAK (TU of Liberec Czech Republic)
T. PIHL (Archimedes Foundation Estonia)
G. POOLA (Artec Design Estonia)
J. RAJSKI (Mentor Graphics USA)
M. ROELOFS (Philips Research Laboratories The Netherlands)
K. VARDANIAN (Yerevan Academy of Sciences Armenia)
Y. ZORIAN (Virage Logic USA) |
|
|
Tuesday, May
24 |
|
|
| 8:30-10:00 |
Session 5 |
| 8:30-10:00 |
Formal Session 5.a: Defect
and Dynamic Fault Testing |
Room Alfa |
| |
Moderators:
S. REDDY (University of Iowa USA), J. RAJSKI (Mentor Graphics USA) |
| |
DOT: New Deterministic
Defect-Oriented ATPG Tool
J. RAIK, R. J. UBAR (Tallinn University of Technology Estonia), J.
SUDBROCK (Darmstadt TU Germany), W. KUZMICZ, W. PLESKACZ (Warsaw UT
Poland) |
| |
Testing Logic Circuits
for Transient Faults
S. KRISHNASWAMY, I. MARKOV, J. HAYES (University of Michigan - USA) |
| |
A Novel Delay Fault
Testing Methodology Using On-Chip Low-Overhead Delay Measurement Hardware
at Strategic Probe Points
A. RAYCHOWDHURY, S. GHOSH, S. BHUNIA, D. GHOSH, K. ROY (Purdue University
- USA) |
| 8:30-10:00 |
Formal Session 5.b: SRAM Memory
Testing |
Room Omega |
| |
Moderators:
Y. ZORIAN (Virage Logic USA), G. DINATALE (Politecnico di Torino Italy) |
| |
Resistive-Open Defect
Influence in SRAM Pre-Charge Circuits: Analysis and Characterization
L. DILILLO, P. GIRARD, S. PRAVOSSOUDOVITCH, A. VIRAZEL (LIRMM - France),
M. BASTIAN HAGE-HASSAN (Infineon Technologies - France) |
| |
Automatic March Tests
Generation for Static and Dynamic Faults in SRAMs
A. BOSIO, A.BENSO, S. DI CARLO, G. DI NATALE, P. PRINETTO (Politecnico
di Torino - Italy) |
| |
A Programmable Time
Measurement Architecture for Embedded Memory Characterization
M. COLLINS, B. AL-HASHIMI, N. ROSS (University of Southampton - United
Kingdom) |
|
|
| 10:00-11:00 |
Poster Session 3 |
|
| |
Test Pattern Compression for Circuits
with the RESPIN Architecture
O. NOVAK, J. ZAHRADKA (Technical University of Liberec Czech Republic) |
| |
An Efficient Test Set Embedding Scheme
with Reduced Test Data Storage and Test Sequence Length Requirements for
Scan-based Testing
D. KASERIDIS, E. KALLIGEROS (University of Patras Greece), X. KAVOUSIANOS
(Univerisity of Ioannina Greece), D. NIKOLOS (University of Patras Greece) |
| |
Evolutionary Approach to Test Generation
for Functional BIST
Y. A. SKOBTSOV (Donetsk National Technical University Ukraine), D.
IVANOV, V. Y. SKOBTSOV (NAS of Ukraine Ukraine), R. J. UBAR, J. RAIK (Tallinn
University of Technology Estonia) |
| |
A Complex Approach to Digital RTL Circuit
Testability - iFCoRT System
R. RUZICKA (Brno University of Technology Czech Republic) |
| |
Impact of Circuit Realization on the Fault
Coverage
E. BAREISA, V. JUSAS, K. MOTIEJUNAS, R. SEINAUSKAS (Kaunas University
of Technology Lithuania) |
| |
Reverse Order Restoration Based on Test
Relaxation and Subsequence Merging for Efficient Static Compaction for Sequential
Circuits
A. EL-MALEH, S. S. KHURSHEED, S. M. SAIT (King Fahd University of Petroleum
and Minerals Saudi Arabia) |
| |
A Cost-Effective Test Flow for Homogeneous
Network-on-Chip: a Case Study
A. AMORY, E. BRIAO, E. COTA, M. LUBASZEWSKI (Federal University of Rio Grande
do Sul Brazil), F. MORAES (PUCRS Brazil) |
| |
Modular and Rapid Testing of SOCs with
Unwrapped Logic Blocks
Q. XU, N. NICOLICI (McMaster University Canada) |
| |
Fault Diagnosis and Fault Model Aliasing
I. POMERANZ (Purdue University USA), S. VENKATARAMAN (Intel Corp.
USA), S. REDDY (University of Iowa USA) |
|
|
| 11:00-12:30 |
Session 6 |
| 11:00-12:30 |
Formal Session 6.a: Testing
Regular Structures |
Room Alfa |
| |
Moderators:
N. TOUBA (University of Texas at Austin USA), H. FUJIWARA (Nara Institute
of Science and Technology Japan) |
| |
Multiple errors produced
by single upsets in FPGA configuration memory:a possible solution
M. VIOLANTE, M. SONZA REORDA, L. STERPONE (Politecnico di Torino - Italy) |
| |
Fault Collapsing for
Flash Memory Disturb Faults
M. MOHAMMAD, L. TERKAWI (Kuwait University Kuwait) |
| |
Low Power Embedded DRAMs
with High Quality Error Correcting Capabilities
P. OEHLER (University of Innsbruck - Austria), S. HELLEBRAND (University
of Paderborn - Germany) |
11:00-12:30 |
Informal Session 6.b: Advances
in Characterization and Diagnosis |
Room Omega |
| |
Moderators:
M. KESSLER (IBM Labor Boeblingen Germany), S. PRAVOSSOUDOVITCH (LIRMM
France) |
| |
X-filter: A Novel Way of Removing the Effect
of Unknowns in Output Response Compactors to Recover the Error Information
M. SHARMA, W.-T. CHENG (Mentor Graphics Corporation USA) |
| |
Sleep Modes - an Enabler for Full-Wafer
Test
B. WEST (Credence Systems Corporation USA) |
| |
Embedded Characterization Technique for
BGA Solder Joint Wear-Out with 1149.4 Mixed Signal Test Bus Architecture
J. VOUTILAINEN, M. MOILANEN (University of Oulu - Finland) |
|
|
12:30-14:00 |
Lunch |
|
|
| 14:00-15:00 |
Session 7 |
| 14:00-15:00 |
Session 7.a: Embedded Tutorial 1 |
Room Alfa |
| |
Moderators:
B. STRAUBE (Fraunhofer EAS/IIS Germany), H. MANHAEVE (Q-Star Test nv
Belgium) |
| |
Understanding Failure Mechanisms and Test
Methods in Nanometer Technologies
J. SEGURA (Balearic Islands University - Spain), C. F. HAWKINGS (The
University of New Mexico - USA) |
14:00-15:00 |
Session 7.b: Embedded Tutorial 2 |
Room Omega |
| |
Moderators:
P. CAUVET (Philips Semiconductors The Netherlands), S. BERNARD (Politecnico
di Torino Italy) |
| |
CMOS Image Sensors and Optical Testing
P. MAXWELL (Agilent Technologies - USA) |
|
|
15:30-
|
Social Event |
|
|
Wednesday,
May 25 |
|
|
| 8:30-10:00 |
Session 8 |
| 8:30-10:00 |
Formal Session 8.a: Validation
and Molecular Electronics |
Room Alfa |
| |
Moderators:
J. ABRAHAM (University of Texas USA), M. SONZA REORDA (Politecnico di
Torino Italy) |
| |
Design Validation of
Behavioral VHDL Descriptions for Arbitrary Fault Models
F. XIN, M. CIESIELSKI (University of Massachusetts - USA), I. HARRIS
(University of California Irvine - USA) |
| |
Coverage of Formal Properties
based on a High-Level Fault Model and Functional ATPG
G. PRAVADELLI, F. FUMMI (University of Verona - Italy), F. TOTO (ST
Microelectronics - Italy) |
| |
Built-In Self-Test of
Molecular Electronics-Based Nanofabrics
K.CHAKRABARTY, Z. WANG (Duke University - USA) |
8:30-10:00 |
Vendor Session 8.b |
Room Omega |
| |
Moderators:
J.L. CARBONERO (FTM / CCDS / DM&T STMicroelectronics France), R. ILLMAN
(Cadence Design Foundry UK) |
| |
Current Testing for Nanotechnologies:
A Demystifying Application Perspective
H. MANHAEVE (Q-Star Test Belgium) |
| |
High Speed I/O Test Challenges
B. WEST, M. LORANGER (Credence Systems Corporation USA) |
| |
High Throughput Scan Testing - A
Novel Approach for Reducing Scan Test Time in Production
M. BRAUN, D.CHINDAMO, M.FISCHER (Agilent Technologies Germany) |
|
|
10:00-11:00 |
Poster Session 4 |
|
| |
RobOps - Arithmetic Operators for Future
Technologies
C. LISBOA, L. CARRO, E. COTA (Universidade federal do Rio Grande do
Sul Brazil) |
| |
Memories with Robust Self Error Detection
and Correction Invariant to Error Distributions
K. KULIKOWSKI, M. KARPOVSKY, A. TAUBIN (Boston University USA) |
| |
Fast Observation Architecture for FPGA-based
SEU Analysis
A. EJLALI, B. AL-HASHIMI (University of Southampton UK), S. G. MIREMADI
(Sharif University of Technology Iran) |
| |
Testing Superconductor Logic Integrated
Circuits
A. JOSEPH, H. KERKHOFF (MESA+ Institute for Nanotechnology The Netherlands) |
| |
Test Data Compression Method through Encoding
Necessary Specified Bits
Y. SHI, S. KIMURA, N. TOGAWA, M. YANAGISAWA, T. OHTSUKI (Waseda University
Japan) |
| |
Linear automata testing subject to uncertainty
of observed reactions
D. SPERANSKIY (Saratov State University Russia) |
| |
Efficient At-Speed Interconnect BIST and
Diagnosis Framework
A. JUTMAN (Tallinn University of Technology Estonia) |
| |
An integrated environment for P1500 compliance
checking
C. TIBALDI, P. PRINETTO, A. BENSO (Politecnico di Torino Italy), Y.
ZORIAN (Virage Logic USA) |
|
|
| 11:00-12:30 |
Session 9 |
| 11:00-12:30 |
Formal Session 9.a: Fault
Diagnosis and Memory Test |
Room Alfa |
| |
Moderators:
E. VAN GEEST (Philips Electronic Design & Tools The Netherlands),
J.M. VRIGNAUD (ATMEL - France) |
| |
Convolutional compaction-driven
diagnosis of scan failures
J. TYSZER (Poznan University of Technology Poland), G. MRUGALSKI (Mentor
Graphics Corporation USA), A. POGIEL (Poznan University of Technology
Poland), J. RAJSKI, C. WANG (Mentor Graphics Corporation USA) |
| |
Stuck-Open Fault Diagnosis
with Stuck-At Model
X. FAN, W. MOORE (Oxford University UK), C. HORA, G. GRONTHOUD (Phlips
Research The Netherlands) |
| |
Thermal Measurements on Memory Modules
G. EGGERS, M. CARMONA, A. LEGEN, A. WOLTER, T. HUBER (Infineon Technologies
AG - Germany) |
11:00-12:30 |
Informal Session 9.b: Dedicated
Test Resources |
Room Omega |
| |
Moderators:
G. CARLSSON (Ericsson Sweden), W. ANHEIER (University of Bremen Germany) |
| |
Silicon-based System-in-Package accelerates
the development of new test technologies and methodologies
P. CAUVET, C. KELMA (Philips Semiconductors The Netherlands) |
| |
Yield Prediction and Evaluation for Embedded
SRAM and Memory System Compilers
K. ALEKSANYAN, V. VARDANIAN (Virage Logic Armenia), Y. ZORIAN (Virage
Logic USA) |
| |
LOW COST HIGH TEMPERATURE TEST (LOCHITT)
SYSTEM
Y. LI, G. RUSSELL, H. BAHR (University of Newcastle upon Tyne UK) |
|
|
12:30-14:00 |
Lunch |
|
|
| 14:00-15:00 |
Session 10 |
| 14:00-15:00 |
Session 10.a: Embedded Tutorial
3 |
Room Alfa |
| |
Moderators:
A. RICHARDSON (Lancaster University - UK), Z. KOTASEK (Brno University of
Technology Czech Republic) |
|
|
Testing of MEMS-based Microsystems
H. G. KERKHOFF (MESA+ Institute for Nanotechnology The Netherlands) |
| 14:00-15:00 |
Session 10.b: Embedded Tutorial
4 |
Room Omega |
| |
Moderators:
M.L. FLOTTES (LIRMM France), O. NOVAK (Technical University of Liberec
Czech Republic) |
|
|
From Embedded Test to Embedded Diagnosis
H.-J. WUNDERLICH (University of Stuttgart - Germany) |
|
|
| 15:00-16:30 |
Session 11 |
| 15:00-16:30 |
Formal Session 11: SOC Testing
and Secure IC |
Room Alfa |
| |
Moderators:
B. ROUZEYRE (LIRMM France), E. LARSSON (Linköping University Sweden) |
| |
Test Control for Secure
Scan Designs
D. HELY (ST Microelectronics/ LIRMM France), M.-L. FLOTTES (LIRMM
France), F. BANCEL (ST Microelectronics France) , B. ROUZEYRE (LIRMM
France) |
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Time-Multiplexed Test
Data Decompression Architecture for Core-Based SOCs with Improved Utilization
of Tester Channels
A. KINSMAN, N. NICOLICI (McMaster University Canada) |
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Exploiting an Infrastructure
IP to reduce the costs of memory diagnosis in SoCs
P. BERNARDI, M. GROSSO, M. SONZA REORDA, M. REBAUDENGO (Politecnico
di Torino - Italy) |
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| 16:30-... |
Closing Session |
Room Alfa |
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Formal Category |
