Lectures

NB! This is the preliminary schedule. That is, names of the topics and their order may change.
Distribution of the content between lectures may change, i.e., the boundaries between lectures are not fixed.

Lectures are scheduled for Fridays from 10:00 to 11:30 (at ICT-315).

Recorded lectures. [Additional codeces mabye needed...]

Week	Date	Topic	.pdf	[2016]
1	2.02	Introduction and modeling principles.
1-3	2.02, 9.02, 16.02	High-level synthesis.
4	23.02	Hardware description language SystemC.
5, 7	2.03, 16.03	Co-modeling and co-simulation of digital systems, testbenches.
6	9.03	Travelling...
8, 10	23.03, 6.04	Hardware description language SystemVerilog.
11, 12	13.04, 20.04	Hardware description languages and RTL synthesis.
13	27.04	Synthesis of digital systems at different abstraction levels.
14	4.05	Modeling of analog and mixed signal systems - SPICE, VHDL-AMS.
15	11.05	Code transformations at system and algorithmic levels.
16	18.05	System level description languages.

'*)' - lecture material from the previous year.
- Portable Document Format. Install to read and print the files.

Extra materials - VHDL handouts.

Last modified 2018.05.18.