Kaks loengut Duke'i ülikooli professorilt7.-8. septembril peab arvutitehnika instituudis kaks loengut tunnustatud Duke'i ülikooli professor Krishnendu (Krish) Chakrabarty. Loengute teemadeks on uudsed, 3D integratsioonil põhinevad kiibid ning mikroelektroonikasüsteemide diagnoos. Loengute abstraktid ning prof. Chakrabarty biograafia on leitavad allpool.
Lisainfo: Gert Jervan
Professor of Electrical and Computer Engineering
129 Hudson Hall, Box 90291
Durham, NC 27708
Phone: +1 919 660 5244
Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively, all in Computer Science and Engineering. He is now Professor of Electrical and Computer Engineering at Duke University.
Prof. Chakrabarty is a Fellow of IEEE, a Senior Member of ACM, and a Member of Sigma Xi. He received a Meritorious Service Award from the IEEE Computer Society in 2008. Prof. Chakrabarty is a recipient of Duke University's 2008 Dean's Award for Excellence in Mentoring. He is also a recipient of the National Science Foundation Early Faculty (CAREER) award (1999) and the Office of Naval Research Young Investigator award (2001).
His current research projects include: testing and design-for-testability of system-on-chip integrated circuits; digital microfluidic biochips; nanotechnology circuits and systems based on DNA self-assembly; delay-tolerant wireless networks.
Prof. Chakrabarty served as a Distinguished Visitor of the IEEE Computer Society for 2005-2007 and as a Distinguished Lecturer of the IEEE Circuits and Systems Society for 2006-2007. Since 2008, he is serving as an ACM Distinguished Speaker. He is an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on VLSI Systems, IEEE Transactions on Biomedical Circuits and Systems, and ACM Journal on Emerging Technologies in Computing Systems, and an Editor of IEEE Design & Test of Computers, and Journal of Electronic Testing: Theory and Applications (JETTA). He recently completed his term as Associate Editor of IEEE Transactions on Circuits and System I (2006-2007). He served as Program Chair for the 2005 IEEE Asian Test Symposium and is the designed General Co-Chair for the 2010 IEEE Asian Test Symposium.
7. september, kell 14:00, ruumis IT-209
Testing of 3D Integrated Circuits: Challenges and Emerging Solutions
Three-dimensional integrated circuits (3D ICs) promise to overcome barriers in interconnect scaling, thereby offering an opportunity to get higher performance using CMOS technology. Despite these benefits, testing remains a major obstacle that hinders the adoption of 3D integration. Test techniques and design-for-testability (DfT) solutions for 3D ICs have remained largely unexplored in the research community, even though experts in industry have identified a number of test challenges related to the lack of probe access for wafers, test access to modules in stacked wafers/dies, thermal concerns, test economics, and new defects arising from unique processing steps such as wafer thinning, alignment, and bonding. In this talk, the speaker will present an overview of 3D integration, its unique processing and assembly steps, testing and DfT challenges, and some of the solutions being advocated for these challenges. The speaker will focus on DfT innovations related to the optimization of die wrappers, test scheduling, and access to dies and inter-die interconnects during stack testing.
8. september, kell 10:00, ruumis IT-209
Dictionary-Based Methods for Board-Level Fault Diagnosis
Increasing integration densities and high operating speeds are leading to subtle manifestations of defects at the board level. Board-level functional test is therefore necessary for product qualification. The diagnosis of functional failures is especially challenging, and the cost associated with board-level diagnosis is escalating rapidly. An effective and cost-efficient board-level diagnosis strategy is needed to reduce manufacturing cost and time-to-market, as well as to improve product quality. In this talk, the speaker will show how Bayesian inference can form the basis for a new board-level diagnosis framework that allows us to identify faulty devices or faulty modules within a device on a failing board with high confidence. Bayesian inference offers a powerful probabilistic method for pattern analysis, classification, and decision making under uncertainty. This inference technique is used by first generating a database of fault syndromes obtained using fault-insertion test at the module pin level on a fault-free board, and then using the database along with the observed erroneous behavior of a failing board to infer the most likely faulty device.
In the second part of the talk, a generic fault-diagnosis method based on an error-flow dictionary will be presented to identify the root cause of functional failures on a chip or board. Error propagation mimics actual dataflow in a circuit, thus it reflects the native (functional) mode of circuit operation. In contrast to conventional fault syndromes, error flow includes the failure information in terms of circuit functionality, which significantly facilitates the diagnosis of functional failures. In the proposed diagnosis procedure, error flow is first learned from a good circuit by intentionally inserting faults, and then the root cause of a failing circuit is determined by comparing the similarity between the pre-learned error flow and the error flow observed from the failing circuit. The similarity of two error flows is evaluated based on the length of the longest common subsequence in string matching. Results wil be presented for an industrial communication circuit.