Facing Challenges in Device, Board and System Level DFT?
Join us for an informative full day seminar (and buffet lunch) on how Boundary-Scan Design-for-Test (DFT) can help you achieve a high level of test coverage and diagnostic resolution on today's complex digital/mixed-signal circuit designs and system architectures.
The seminar will be presented at the following time and venues:
- October 21, Tallinn click here to register
- October 22, Tampere click here to register
- October 23, Oulu click here to register
The seminar includes these important topics:
- IEEE 1532 (In-system Configuration) Principles
- Board Level Boundary-Scan Design-For-Test considerations
- Device Level DFT including Embedded Test Concepts
- Implementing Embedded Test solutions within Platform FPGA designs
- System Level Architecture considerations
- Boundary-scan System Test Access solutions
- Test Challenges with LVDS (including at-speed interconnect testing &1149.6)
- Analog & mixed-signal boundary-scan
Speakers will be from:
- JTAG Technologies
- National Semiconductor
- Xilinx, Insight Memec
Attendees should have prior familiarity with the principles of boundary-scan (although a brief overview will be presented). Once we receive your registration you will receive confirmation, agenda and venue details.