San Diego professori Alex Orailoglu loeng Self-Test for State-of-the-art VLSI DesignsKolmapäeval, 06.09.2006 toimub San Diego professori Alex Orailoglu loeng Self-Test for
State-of-the-art VLSI Designs.
Toimumiskoht VI-223: (TTÜ peahoone 6. korpus),
Prof. Alex Orailoglu külastab TTÜ-d kui IEEE distinguished lecturer.
Design for test methodologies, particularly Built-in Self-test (BIST), are playing an increasingly significant role in managing the test cost of current designs. To reap the significant cost reduction benefits of BIST in test generation and test application, possible deterioration in terms of fault coverage levels and diagnostic capabilities, due to random resistant faults and limited response information, needs to be averted.
We outline initially an investigation of on-chip pseudo-random test pattern generators and of methodologies for selection of suitable pattern generators for VLSI designs. We follow this up with a study of methodologies for reducing the cost of deterministic test pattern application. On the fault diagnosis side, eficient fault diagnosis approaches are proposed for scan-based BIST designs. Improvements in information extraction from the BIST signature are attained through utilization of both superior deterministic partitioning schemes and enhanced analysis procedures. The talk continues with an investigation of concurrent test for linear digital systems. A low-cost, accumulation based concurrent error detection scheme provides considerable benefits through observation of the average behavior of the system and through careful gate level fault effect consideration. The
significant benefits provided by the techniques proposed are attained at negligible hardware costs, ensuring the continued dominance of on-chip test techniques for state-of-the-art VLSI designs.
Alex Orailoglu received his S.B. Degree cum laude from Harvard University in Applied Mathematics and his M.S. and Ph.D. degrees in Computer Science from the University of Illinois, Urbana-Champaign. Alex Orailoglu is currently a Professor of Computer Science and Engineering at the University of California, San Diego. His research interests include Embedded Systems and Processors, digital and analog test, fault tolerant computing,
Computer-Aided Design, and nanoelectronics. Professor Orailoglu serves in the technical, organizing and/or steering committees of the major VLSI Test, Design Automation, Embedded Systems and Computer Architecture conferences and workshops. He is an associate editor of the IEEE Design and Test Magazine, of the Journal of Electronic
Test: Theory and Applications, of the IEE Digital Systems and Design Journal, and of the Journal of Embedded Computing. He has served as the Technical Program Chair of the 1998 High Level Design Validation and Test (HLDVT) Workshop, as the General Chair of HLDVT'99, as the Technical Program Co-Chair of the 2003 CODES/ISSS (ACM/IEEE Hardware Soft- ware Codesign Symposium & ACM/IEEE International System Synthesis Symposium), as the General Chair of CODES+ISSS '04, as the Program Co-Chair of the 18th Symposium on Integrated Circuits and Systems Design (SBCCI 2005), as the
Program Chair of the IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NanoArch 2005), as the Program Chair of the Workshop on Application Specic Pro- cessors (WASP 2005), and as the Vice Program Co-Chair of the 2004 VLSI Test Symposium and of the 2005 VLSI Test Symposium. He currently serves as the Vice Program Co-Chair of the 2006 VLSI Test Symposium.
Professor Orailoglu is the founding chair of the Workshop on Application Specic Processors (WASP), and has also served as its General and Program Chair in 2002 and 2003. He is also the founding chair of the IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NanoArch). Dr. Orailogate level fault etechniques glu currently serves on more than 20 Program Committees of technical meetings in the areas of VLSI Test, Embedded Systems, Computer Architectures, and
Nanoelectronics and also serves on multiple steering committees.
Professor Orailoglu has served as a member of the IEEE Test Technology Technical Council (TTTC) Executive Committee, as the Vice Chair of TTTC, as the Chair of the Test Technology Education Program group, as the Technical Activities Committee Chair and Planning Co-Chair of TTTC.
He currently serves as the Communities Chair of the IEEE Computer Society Technical Activities Board. He is the founding chair of the IEEE Computer Society Task Force on Hardware/Software Codesign.
Dr. Orailoglu has published 200 research articles and is a Golden Core member of the IEEE Computer Society.