Loeng teemal "Communication Performance in Networks on Chip"Neljapäev, 05. oktoober 2006
Lektor: Axel Jantsch
The seminar will systematically discuss (1) the main elements in a network i.e. the network interface the switch and the link, and (2) the main issues in communication networks: topology, routing, switching, flow control and offered communication services. The significance and effect of a two dimensional VLSI implementation will be emphasized throughout the tutorial.
Various possible network topologies will be discussed such as k-ary n-cubes, trees, fat trees, butterflies and Benes networks. Their relation will be analyst with the conclusion that all of them can be mapped to a k-ary n-cube n a straight forward and predictable way. As
a consequence the k-ary n-cube serves as a canonical model for performance analysis that is relevant for all other topologies.
The most important routing schemes such as source based routing table based routing and various deterministic and adaptive routing schemes will be elaborated.
In a similar manner all important switching techniques such as store-and-forward, virtual cut through, and wormhole switching will be explained and analyst.
The basic switch-to-switch and end-to-end flow control mechanisms such as acknowledgment based, credit based and watermark based techniques.
A network can offer best effort, maximum latency, minimum bandwidth and maximum jitter communication services or a mixture of these. The seminar will present the basic techniques to provide QoS.
In order to analyze performance, several key performance parameters such as latency, bandwidth and cost for wires and switches will be introduced. Then the impact of many of the main network parameters on performance will be analyzed based on closed formulas and simulation. For instance the effect of different topologies, routing and switching schemes, wire delays, bus width, switch complexity, message size, contention and offered services on the performance will be discussed and illustrated in numerous plots.
Axel Jantsch received a Dipl.Ing. (1988) and a Dr. Tech. (1992) degree from the Technical University Vienna. Between 1993 and 1995 he received the Alfred Schrödinger scholarship from the Austrian Science Foundation as a guest researcher at the Royal Institute of
Technology (KTH). From 1995 through 1997 he was with Siemens Austria in Vienna as a system validation engineer. Since 2002 he is full professor in Electronic System Design at KTH. A. Jantsch has published over 130 papers in international conferences and journals and three book in the areas of VLSI design and synthesis, system level specification, modelling and validation, HW/ SW codesign and cosynthesis, reconfigurable computing and networks on chip. He has served on a number of technical program committees of international conferences such as FDL, DATE, CODES+ISSS, SOC, and HDLCON and others. He has been TPC chair of SSDL/FDL 2000, TPC co-chair of CODES+ISSS 2004 and general chair of CODES+ISSS 2005. Since December 2002 he is Subject Area Editor for the Journal of System Architecture.
At the Royal Institye of Technology A. Jantsch is heading a number of research projects involving a total number of 10 Ph.D. students, in the areas of system level specification, design, synthesis, validation and networks on chip. From January 1999 till December 2002 he has been program manager of the SSF funded research program Integrated Electronic Systems involving a total number of 50 Ph.D. students at four Universities. Since January 2004 he is head of the Laboratory of Electronics and Computer Systems.