Turbo Tester - A CAD Software for DigitalTest
Turbo Tester (TT) is a test software package developed at the Department of Computer Engineering of Tallinn University of Technology. The TT software consists of the following test tools: test generation by different algorithms, test set optimization, fault simulation for combinational and sequential circuits, testability analysis and fault diagnosis. It includes test generators, logic and fault simulators, a test optimizer, a module for hazard analysis, BIST architecture simulators, design verification and design error diagnosis tools.
xTractor is a small set of experimental programs dedicated for High Level Synthesis of CMIST (control and memory instensive systems) style applications. All programs take input in IRSYD, manipulate with it and output the resulting IRSYD. One of the programs (xfc2hdl) generates RT Level VHDL or Verilog code which can be used by Logic Level synthesis tools. The generated HDL code is Synopsys DC oriented currently.
DefSim – Feel the silicon reality!
DefSim is an integrated circuit (IC) and a measurement environment for experimental study of CMOS defects. The central element of the DefSim environment is an educational IC with a large variety of shorts and opens physically inserted into a set of simple digital circuits. The IC is attached to a dedicated measurement box serving as an interface to the computer. The box supports two measurement modes - voltage and IDDQ testing.
BIST Analyzer – Scan your mind!
BIST Analyzer is a training system aimed at teaching main (both basic and advanced) principles and techniques applied in self-testing (BIST) of modern multi-core electronic systems. BIST Analyzer facilitates study of various test optimization problems, allows fault coverage analysis for arbitrary circuits and with various test generation and optimization parameters. The tool illustrates the working principles of Pseudo-Random Test Pattern Generators (PRPG), gives students a hands-on experience on designing, optimizing and using them as a stand-alone solution as well as in combination with deterministic and other off-chip test generators.
- Contact person: Artur Jutman
Trainer 1149 - A doorway into the Boundary Scan
Trainer 1149 is a multi-functional software system, which provides a simulation, demonstration, and CAD environment for learning, research, and development related to IEEE 1149.1 Boundary Scan (BS) standard. The system supports important Boundary Scan data formats (BSDL, SVF) through which it can interact with other BS development tools. At the same time, the system allows a visual design and simulation of BS-enabled chips, non-BS clusters and whole boards. It is also possible to simulate the behavior of various interconnect faults and inspect them using interactive tools.
- Applet: http://www.pld.ttu.ee/applets/bs/
- Application: http://www.testonica.com/1149/
- Contact person: Artur Jutman
Applets for training and teaching logic synthesis and test
A set of applets are available for self-learning, training and teaching various aspects of decomposition and test of digital circuits and systems. In the field of test the topics of logic and register transfer level testing (fault simulation, test generation, fault diagnosis), boundary scan and built-in self-test are covered. For logic synthesis several problems of decomposition of finite state machines are illustrated and solutions are demonstrated. A big reservoir of simple example circuits is given to train on the screen in interactive mode the main important techniques and algorithms. The software provides easy action and reaction (click and watch), the possibility of distance learning, and learning by doing.
Software Environment for FSM Decomposition and Synthesis
This software package is aimed to organize an environment for research and study of various methods of decomposition of Finite State Machines (FSM). The system consists of several modules that support different algorithms of decomposition: multiplicative decomposition, additive decomposition and generalized additive decomposition. The system is capable to decompose source FSM for meeting specific constraints, synthesize network of interacting sub-FSMs, perform network encoding, analyze steady-state probabilities, etc. Although the software already contains built-in library of benchmarks, several well-known FSM description formats (KISS2, BLIF, VHDL) are also supported. The modules of the system are accessible over Internet, thus it is possible to run experiments just in web-browser. The interactive modules (together with additional information and the theoretical basics of decomposition) are located at the following URLs:
- Contact person: Sergei Devadze
SSBDD Visualizer is a tool that allows entry, editing, zooming and integrity Check of Structurally Synthesized BDD models. It can also be used for highlighting paths and/or nodes in SSBDDs. The tool can read and write AGM format supported by the Turbo Tester tool set.
- Contact person: Jaan Raik
Deterministic traffic generator for NoC simulator
Network-on-Chip is an emerging paradigm to address future System-on-Chip design challenges. This approach offers to a NoC designer a flexible, scalable, and unified communication platform. We have developed a deterministic traffic generator module for the Nostrum NoC simulator NNSE that is developed in Royal Institute of Technology (Stockholm, Sweden). Deterministic traffic generator module allows a NoC designer to specify the source, destination node, simulation cycle when to send, and the amount of data. The whole simulation process is integrated into the graphical user interface written in Python. One could configure the network, traffic, simulate, and view the simulation results. It is possible to feed in to the simulator a traffic configuration file generated by another application. An XML interface is used for that purpose. It offers integration possibility between another Network-on-Chip design software. The NNSE NoC simulation environment could be used in the university subjects related with System-on-Chip design.
- Contact person: Gert Jervan
Test Time Calculator (Simple NoC simulator, based on XY-routing)
Test Time Calculator (TTC) can be used for recalculating given test schedules such that the specifics of the given NoC are taken into account. The input/output formats are compliant with Nostrum NNSE.
- Contact person: Gert Jervan