Estonian Science Foundation grants
ESF grant 9429: Self-Testing Dependable Mesochronous Network-on-Chips
- Contact person: prof. Jaan Raik
Electronics industry has entered the nanometer era, where the complexity of circuits has reached new levels. Modern circuits are consisting of hundreds of modules, or cores, and of billions of transistors. It is increasingly difficult to design and test systems of such a high complexity. In order to contend the challenge, the Network-on-a-Chip (NoC) paradigm has emerged. NoC is replacing traditional bus architectures and providing higher bandwidth, lower latency and a scalable communication infrastructure for modern electronic systems. The NoC paradigm is based on packet-switched networks implemented on the chip. This provides a parallelism in communication architectures that can be utilized by the application mapped onto the network. The same parallel infrastructure also inserts routing redundancy to the system by allowing broken connections to be avoided and packages to be rerouted via alternative paths. Thus, a very natural scheme for graceful degradation in NoCs would be to reconfigure the routers in the network by switching off the faulty links. This reconfiguration can be applied either off-line after the post-manufacturing test, or on-line, during the normal operation of the chip. Current research grant is going to surpass the state-of-the-art by developing an integrated approach to fault tolerance that will take into account different aspects of such graceful degradation scheme. This will include the application layer, the routing algorithm, the reconfiguration management and core isolation during test. In addition, dedicated methods for NoC test will be developed. Despite of a large number of recent research works the problem of testing NoCs is still a challenge that lacks an efficient solution. Existing approaches relying on the use of standard design-for-testability solutions result in a prohibitively large area overhead and poor utilization of NoCs own high-performance, parallel routing infrastructure as the test access mechanism. In this project we will build on our experience in developing functional fault model based test methods for NoC. These methods will be further developed to support the self-test of mesochronous networks and irregular topologies as well as to handle the different control structures in the NoC switches. The grant project is going to be carried out in close co-operation with top-level experts in this field. The partners include Univ. of Ferrara, IHP Frankfurt Oder, TU Darmstadt, TU Cottbus, KTH Stockholm and TU Potsdam.
ESF grant 9423: Chip-Embedded Instrumentation for Testing of Complex Electronic Systems
- Contact person: Sergei Devadze
Today, the microelectronics is the one of the most blossoming sectors of global industry. The ubiquity of digital systems made modern society to be extremely dependant on correct operation of surrounding devices. As a result, this brings the issues of reliability of electronics in the forefront. In order to ensure the flawless functioning, each of the manufactured electronic products needs to be thoroughly tested. However, manufacturing defect testing turns to be a challenging task due to the growing complexity, ceaseless miniaturization and increasing performance of modern microelectronic devices. The current grant application focuses on improving of testability of emerging high-performance systems and advanced printed circuit boards (PCBs). Although, the issues of PCB testing were being addressed by academic and engineering communities for several decades, the presented application aims to a completely new niche in science and technology: automated test with a help of chip embedded instruments. The outcome of the project is a methodology for generation of parametrizable and customizable embedded test instrument IP cores. The development of embedded instrumentation is targeted to solve many unsolved challenges in the area board- and system-level test (e.g. at-speed test of high-speed components, structural test and diagnosis of delay and transition faults, etc). Moreover, the methodology developed within the scope of current project will reduce the overall test costs due to replacement of expensive Automated Test Equipment with relatively cheap embedded virtual instruments. Current grant proposal was encouraged by the significant interest to the presented topic shown by industrial companies in the microelectronic field. In view of this fact, the technology based on results of the project is directly applicable in the national and global microelectronics manufacturing industry.
ESF grant 9251 Reconfigurable Processor for Problems of Combinatorial Computations over Tree-like Data Structures
- Contact person: Aleksander Sudnitsõn
There are many practical applications that require solution of combinatorial problems. Majority of these problems are NP-complete and as a result they are very time and resource consuming. Reconfigurable processor for problems of combinatorial computations, that is going to be designed on the basis of deep theoretical investigations, will permit to reduce the required resources with the aid of optimization technique for reconfigurable digital systems. The idea is to apply combinatorial technique for a reasonable number of data and to combine this technique with pointer-based data structures, such as tree-like structures. An important advantage of tree-like structures compared to other known models is an opportunity of rapid adaptation to potential modifications that is very important for implementation of data stream processing. Recently, novel methods for combinatorial computations over tree-like structures and their implementation in hardware have been proposed as a team-work of researchers from Aveiro University and the applicant of this project. The advantages of the proposed techniques were demonstrated through simulation in software, prototyping in FPGA, and experiments. Complex combinatorial computations will be implemented in application-specific architecture of the processor which can execute a matrix-oriented subset of primary operations. The processor will be constructed on the basis of commercially available FPGAs. Note that the best result for the considered computations can be achieved if many different elements are taken into account, such as optimal partitioning the problem between general-purpose software and application specific reconfigurable hardware, methods of interactions and data exchange between software and reconfigurable hardware, computational technique, such as either recursive or iterative, using dedicated circuits for matrix specific computations, low-power design. All this factors are going to be carefully investigated and the relevant proposals based on theoretical and experimental proofs will be formulated. Studies will be conducted in close collaboration with the DETI/IEETA, University of Aveiro (Portugal). Potentially results would be used by organizations involved to Competence Centre in Electronics-, Info- and Communication Technologies ELIKO and Centre for Integrated Electronic Systems and Biomedical Engineering - CEBE.