1st International Workshop on Resilience in Nanoelectronics Systems
September 28-29, 2016
Tallinn, Estonia


Matteo SONZA REORDA, Pol. di Torino, IT


Artur JUTMAN, Testonica Lab, ET
Jaan RAIK, Tallinn UT, ET


Maksim JENIHHIN, Tallinn UT, ET


  • E. Arbel, IBM
  • R. Bloem, Graz UT
  • G. Fey, DLR
  • S. Hamdioui, Delft UT
  • A. Jutman, Testonica
  • H. Kerkhoff, U. Twente
  • R. Krenz-Baath, Hamm-Lippstadt UAS
  • E. Larsson, U. Lund
  • C. Laudert, Infineon
  • C. Lotz, Aster
  • J. Raik, Tallinn UT
  • M. Sonza Reorda, Pol. Torino
  • K. Sunesen, Recore

The Workshop is organized by


Mutual learning to enhance scientific excellence in nanoelectronics based dependable cyber-physical systems (http://www.h2020-tutorial.net)



Board and SoC Test Instrumentation for Ageing and No Failure Found (http://fp7-bastion.eu)



Integrated Modelling, Fault Management, Verification and Reliable Design Environment for Cyber-Physical Systems (http://www.h2020-immortal.eu)



Co-funded by European Union


The workshop is co-located with the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2016. Please visit VLSI-SoC'16 website for registration and accommodation info. (http://www.vlsi-soc.com).


1st International Workshop on Resilience in Nanoelectronics Systems (RENS'16) will be held as a fringe event of VLSI-SoC'16.


Advanced multifunctional computing systems realized in nanoelectronic technologies hold the promise of a significant increase of the computational capability that will offer end-users ever improving services and functionalities (e.g., next generation mobile devices, cloud services, embedded systems etc. However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable posing a threat to our society that is depending on the computers and electronic devices in every aspect of human activities. Hence new techniques introducing resilience into the nanoelectronics systems taking into account the specific requirements of different domains are urgently needed.

This tutorial-style workshop delivers a broad overview of the cutting-edge topics in the area af nanoelectronic systems' resilience. It provides a unique chance to join experts from three on-going European projects as well as researchers working in the area of reliable electronic system design. The topics that will be covered include, but are not limited to, aging modeling, life-time prediction, error-checking, embedded instruments for system health monitoring, fault management, resilient many-core architectures, design validation/verification and automated debug.

RENS'16 will include a keynote, embedded tutorials from 3 EU projects (Horizon 2020 Twinning Action TUTORIAL, FP7 STREP BASTION and Horizon 2020 RIA IMMORTAL), a panel, a special session, posters and demonstrations as well as social activities.

Call for Posters/Demonstrations

The RENS Workshop is looking forward to poster presentations and tool demonstrations. All the contributions to be e-mailed as one page extended abstract to jaan@ati.ttu.ee by July 31st.


Workshop Venue/Registration

RENS'16 Workshop takes place in Park Inn by Radisson Meriton Conference & Spa Hotel Tallinn. Registration should be done at the VLSI-SoC'16 Registration Page.


Wednesday, September 28th

15:45 - 16:30 Welcome (M. Sonza Reorda POLITO; A. Jutman, Testonica; J. Raik, Tallinn UT)

16:30 - 18:00 Keynote: Said Hamdioui (Delft UT, NL) IC Technology and Computing: The Good, The Bad and The Challenging

18:00 - 18:15 Coffee Break

18:15 - 19:30 Wine and Cheese Panel

Moderator: A. Jutman (Testonica Lab)

19:30 - 22:00 Welcome Reception


Thursday, September 29th

9:00 - 9:30 Invited talk: Victor Champac (INAOE, MX)
Screening Reliability Defects in Emerging Technology Nodes

9.30 - 10.30 Embedded tutorial: Hans Kerkhoff (U Twente, NL); Kim Sunesen, Gerard Rauwerda (Recore Systems, NL) Highly dependable many-core SoCs by lifetime prediction and embedded instrumentation

10.30 - 11.00 Posters/Coffee

11.00 - 11.30 Eli Arbel, Shiri Moran (IBM, IL); Roderick Bloem, Franz Röck (Graz UT, AT); Jaan Raik, Ranganathan Hariharan (Tallinn UT, ET) Advances in checker verification

11.30 - 12.30 Embedded tutorial: Paolo Bernardi (POLITO, IT) Stress measurement for burn-in testing

12.30 - 14.00 Lunch

14.00 - 14.30 Invited talk: Heinrich Theodor Vierhaus (BTU Cottbus, DE) Migrating from circuit level error correction to system level error resilience

14.30 - 15.30 Embedded tutorial: Heinz Riener, Jan Malburg, Görschwin Fey (German Aerospace Center (DLR)/University of Bremen, DE) Tool Support for Design Understanding

15.30 - 16.00 Posters/Coffee

16.00 - 16.30 Invited talk: Raimund Ubar (Tallinn UT, ET) Angel's Approach to Digital Testing with Decision Diagrams

16.30 - 16.40 Closing