IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
VLSI-SoC 2016
September 26-28, 2016 Tallinn, ESTONIA

Program

Conference Program in PDF (1.8MB)

 

Conference Rooms

The conference is held in the Peterson I and III rooms at the 2nd floor of the conference hotel:

 

Monday, September 26

8:30 - ...             Registration

9:00 - 9:30         Opening Session

9:30 - 10:30       Keynote I: "Emerging Trends in Nano-Architectures", Giovanni De Micheli, EPF Lausanne, Switzerland

Moderator: Jaan Raik, Tallinn University of Technology, Estonia

10:30 - 11:00    Coffee break

11:00 - 12:40     Session 1a: Multi-Core, 3D and Reconfigurable Architectures

Moderator: Ali Afzali-Kusha, Tehran University, Iran

  • Power-Efficient and Slew-Aware Three Dimensional Gated Clock Tree Synthesis, Minghao Lin, Heming Sun and Shinji Kimura, Waseda University, Kitakyushu, Japan.
  • Dynamic Clock Synchronization Scheme between Voltage Domains in Multi-core Architecture, Jaehyun Kim1, Kiyoung Choi1, Sangheon Lee2 and Soojung Ryu2, 1Seoul National University, Seoul, Korea, 2Samsung Advanced Institute of Technology, Suwon, Korea.
  • Power-Aware Test-time Optimization for Core-Based 3D-SOCs under TSV-Constraints, Sabyasachee Banerjee1, Subhashis Majumder1 and Bhargab Bhattacharya2, 1Heritage Institute of Technology, Kolkata, India, 2Indian Statistical Institute, Kolkata, India.
  • Design of a Multi-Style and Multi-Frequency FPGA, Jotham Vaddaboina Manoranjan, Solomon Surya Tej Mano Sajjan, Vivek Gujari and Kenneth S. Stevens, University of Utah, US.

11:00 - 12:40     Session 1b: Analog and Mixed-Signal IC Design 

Moderator:  Salvador Mir, TIMA, France

  • A 1.62 µW 8-Channel Ultra-High Input Impedance EEG Amplifier for Dry and Non-Contact Biopotential Recording Applications, Mahshid Nasserian1, Ali Peiravi1 and Farshad Moradi2, 1Ferdowsi University of Mashhad, Iran, 2Aarhus University, Denmark.
  • An Efficient Multi Channel, 425µW QPSK Transmitter with Tuning for Process Variation in the Medical Implantable Communications Service (MICS) Band of 4Q2-405MHz, Abhiram Reddy Gundla and Tom Chen, Colorado State University, US.
  • A Low-Power Analog Front-End Neural Acquisition Design for Seizure Detection, Mohammad Tohidi, Jens Kargaard Madsen, Martijn Heck and Farshad Moradi, Aarhus University, Denmark.

12:40 - 14:00     Lunch

14:00 - 15:30     Special Session A: Next Generation Internet of Things: Devices to Architectures

Chairs:  Vijaykrishnan Narayanan, The Pennsylvania State University, US; Matteo Sonza Reorda, Politecnico di Torino, Italy.

  • Enabling Internet-of-Things: Opportunities Brought by Emerging Devices, Circuits, and Architectures, Xueqing Li, Kaisheng Ma, Sumitha George, Johh Sampson and Vijaykrishnan Narayanan, The Pennsylvania State University, US.
  • Design of Nonvolatile Processors and Applications, Fang Su1, Zhibo Wang1, Jinyang Li1, Meng-Fan Chang2 and Yongpan Liu1, 1Tsinghua University, China, 2National Tsing Hua University, Taiwan.
  • Redesigning Software and Systems for Non-volatile Processors on Self-powered Devices, Mengying Zhao1, Keni Qiu2, Yuan Xie3 and Chun Jason Xue4, 1Shandong University, China, 2Capital Normal University, China, 3University of California, Santa Barbara, US, 4University of Hong Kong, Hong Kong.       

14:00 - 15:30     Special Session B: Reducing Functional Safety Verification Complexity

Chairs:  Wolfgang Ecker Infineon, Munich, Germany; Wolfgang Müller, Heinz Nixdorf Institut, Paderborn, Germany.

  • Fast Dynamic Fault Injection for Virtual Microcontroller Platforms, Peer Adelt, Bastian Koppelmann, Wolfgang Müller, Markus Becker, Bernd Kleinjohann, Christoph Scheytt, Paderborn University, Germany.
  • Efficient handling of the Fault Space in Functional Safety Analysis utilizing Formal Methods, Alessandro Bernardini1, Wolfgang Ecker2 and Ulf Schlichtmann1, 1Technical University of Munich, 2Infineon Technologies, Germany.
  • Speeding up Safety Verification by Fault Abstraction and Simulation to Transaction Level, Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, Infineon Technologies, Germany.

15:30 - 16:30     Coffee break / Poster Session 1

  • Frequency Domain Characterization of Batteries for the Design of Energy Storage Subsystems, Yukai Chen, Enrico Macii and Massimo Poncino, Politecnico di Torino, Italy.
  • Static Energy Reduction by Performance Linked Dynamic Cache Resizing, Shounak Chakraborty and Hemangee K. Kapoor, IIT Guwahati, India.
  • Opportunistic Circuit-Switching for Energy Efficient On-Chip Networks, Yuan He and Masaaki Kondo, The University of Tokyo, Japan.
  • Restricting writes for energy-efficient hybrid cache in multi-core architectures, Sukarn Agarwal and Hemangee K. Kapoor, IIT Guwahati, India.
  • A Passive Equalizer and Its Design Methodology for Global Interconnects in VLSIs, Moritoshi Yasunaga1, Naoki Yokoshima1, Ikuo Yoshihara2, 1University of Tsukuba, 2Miyazaki University, Japan.
  • An FPGA-based Testing Platform for the Validation of Automotive Powertrain ECU, Luca Sterpone and Boyang Du, Politecnico di Torino, Italy.
  • A VLSI Architecture for Real-Time Gradient Guided Image Filtering, Lei Wu and Ching Chuen Jong, Nanyang Technological University, Singapore.

16:30 - 18:00     Panel "Horizon 2050 - Chip design in 35 years from now"

Moderator: Graziano Pravadelli, University of Verona, Italy

Panelists:

  • Masahiro Fujita, Tokyo University, Japan
  • Kiyoung Choi, Seoul National University, Korea
  • Ian O'Connor, Lyon Institute of Nanotechnology, France
  • Zainalabedin Navabi, Tehran University, Iran

19:00 - 22:00     Welcome Reception at the Seaplane Harbour

 

Tuesday, September 27

9:00 - 10:00       Keynote II: "From FinFETs to Monolithic 3D Integration", Niraj K. Jha, Princeton University, USA

Moderator: Thomas Hollstein, Tallinn University of Technology, Estonia

10:00 - 10:30     PhD Forum Short Presentations

Moderator: Mario Shölzel, IHP/Potsdam University, Germany

10:30 - 11:10     Coffee break / PhD Forum Poster Session

  • Performance Constrained Static Energy Reduction in Tiled CMP Caches, Shounak Chakraborty,  Indian Institute of Technology Guwahati, India.
  • A SAT-based Scheduling Framework for Multi-Processor Systems on Chips, Christian Schöler, Hochschule Hamm-Lippstadt, Germany.
  • Error Compensation and Self-Repair for FPGA-based Processors, Farnoosh Hosseinzadeh,  BTU Cottbus-Senftenberg, Germany.
  • A Metric-Guided Circuit Design Methodology for Aging Guardband Compensation, Andres Gomez, National Institute for Astrophysics, Optics and Electronics - INAOE, Mexico.
  • A Method of EFSM Model Extraction from HDL Descriptions: Application to Hybrid Verification, Sergey Smolov, Institute for System Programming of Russian Academy of Sciences, Russia.
  • Hardware Implementation of a Spiking Neural P based Multiplier, Carlos Díaz, Instituto Politecnico Nacional, Mexico.
  • A fully integrated 2.4GHz phase shifter for an enhanced SoC solution, Giulio D'Amato,  Politecnico di Bari, Italy.
  • Frame-level Redundancy Scrubbing Technique for SRAM-based FPGAs, Jorge Tonfat, Universidade Federal do Rio Grande do Sul – UFRGS, Brazil.
  • Exploration of Reliability-oriented Design Techniques for Multicore Systems, Felipe Rocha da Rosa, Universidade Federal do Rio Grande do Sul – UFRGS, Brazil.
  • LBDR3D: Logic-Based Distributed Routing for Partially Vertically Connected 3D Network-on-Chips, Behrad Niazmand, Tallinn University of Technology, Estonia.

11:10 - 12:25     Session 2a: Verification and Modeling

Moderator: Dominique Borrione, TIMA, France

  • Conclusively Verifying Clock-Domain Crossings in Very Large Hardware Designs, Guillaume Plassan1,2, Hans-Jörg Peter1, Katell Morin-Allory2, Fahim Rahim1, Shaker Sarwary1 and Dominique Borrione2, 1Synopsys Inc, 2TIMA Laboratory, France.
  • Automatically Comparing Analog Behavior using Earth Mover's Distance, Alexander W. Rath, Sebastian Simon, Volkan Esen and Wolfgang Ecker, Infineon Technologies, Germany.
  • Stimuli Generation through Invariant Mining for Black-Box Verification, Luca Piccolboni and Graziano Pravadelli, University of Verona, Italy.

11:10 - 12:25     Session 2b: Embedded and Cyber-Physical Systems, IoT 

Moderator: Andrea Calimera, Politecnico di Torino, Italy

  • SoC Oriented Real-time High-quality Stereo Vision System, Yanzhe Li1, Kai Huang1 and Luc Claesen2, 1Zhejiang University, Hangzhou, China, 2Hasselt University, Belgium.
  • WCET Overapproximation for Software in the Context of a Cyber-Physical System, Niklas Krafczyk, Heinz Riener and Görschwin Fey, University of Bremen/DLR, Germany.
  • Automatic Protocol Configuration in Single-channel. Low-power Dynamic Signaling for IoT Devices, Shahzad Muzaffar, Numan Saeed and Ibrahim Elfadel, Masdar Institute of Science and Technology, UAE.

12:25 - 13:30     Lunch

13:30 - 14:20     Session 3a: Signal Processing and Communication

Moderator: Ibrahim Elfadel, Masdar Institute of Science and Technology, UAE

  • Low Latency Approximate Matrix Inversion for 46 High Throughput Linear Precoders in Massive MIMO, Abbas Syed Mohsin and Chi-Ying Tsui, Hong Kong University of Science and Technology, Hong Kong.
  • The multi-channel small signal readout system for THz spectroscopy and imaging applications, Dariusz Obrebski1, Cezary Kolacinski1, Michal Zbiec1 and Przemyslaw Zagrajek2, 1Institute of Electron Technology, Poland, 2Military University of Technology, Poland.

13:30 - 14:20     Session 3b: Memory Technologies

Moderator: Said Hamdioui, Delft University of Technology, Netherlands

  • Power and Energy Reduction of Racetrack-based Caches bv Exploiting Shared Shift Operations, Seyed Saber Nabavi Larimi1, Mehdi Kamal1, Ali Afzali-Kusha1 and Hamid Mahmoodi2, 1University of Tehran, Iran, 2San Francisco State University, US.
  • Logic Design with Unipolar Memristors, Avishay Drori, Elad Amrani and Shahar Kvatinsky, Technion - Israel Institute of Technology, Israel.

14:50 - 22:00     Social Event

  • Old Town excursion
  • Gala dinner at the Estonian Open Air Museum

 

Wednesday, September 28

9:00 - 10:00       Keynote III: "From reliability to SoC-level fault management", Artur Jutman, Testonica Lab, Estonia

Moderator: Matteo Sonza Reorda, Politecnico di Torino, Italy

10:00 - 11:00     Coffee break / Poster Session 2

  • An Adaptive Energy-Efficient Task Scheduling under Execution Time Variation based on Statistical Analysis, Takashi Nakada1, Tomoki Hatanaka1, Hiroshi Ueki2, Masanori Hayashikoshi2, Toru Shimizu3 and Hiroshi Nakamura1, 1The University of Tokyo, 2Renesas Electronic Corporation, 3Keio University, Japan.
  • A Compact, Ultra-Low Power AES-CCM IP Core for Wireless Body Area Networks, Van-Phuc Hoang1, Thi-Thanh-Dung Phan1, Van-Lan Dao1 and Cong-Kha Pham2, 1Le Quy Don Technical University, Vietnam, 2The University of Electro-Communications, Japan.
  • XbarGen: a Memristor Based Boolean Logic Synthesis tool, Marcello Traiola1, Mario Barbareschi1, Alberto Bosio2 and Antonino Mazzeo1, 1University of Naples, Italy, 2LIRMM, Université Montpellier, France.
  • Enabling In-Memory Computation of Binary BLAS using ReRAM Crossbar Arrays, Debjyoti Bhattacharjee, Farhad Merchant and Anupam Chattopadhyay, Nanyang Technological University, Singapore.
  • Integrated Soft Error Resilience and Self-Test, Erol Koser, Sebastian Kroesche and Walter Stechele, Technische Universität München, Germany.
  • Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience, Mini Jayakrishnan, Alan Chang and Kim Tae-Hyoung, Nanyang Technological University/NXP Semiconductors, Singapore.
  • Optimistic Clock Adjustment for Preventing Better-Than-Worst-Case Violations, Seyedeh Hanieh Hashemi, Reza Namazian and Zainalabedin Navabi, University of Tehran, Iran.

11:00 - 12:15     Session 4a: Fault Tolerance

Moderator: Raimund Ubar, Tallinn University of Technology, Estonia

  • Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs, Yi Zhao1, Saqib Khursheed2, Bashir M. Al-Hashimi3, Zhiwen Zhao4, 1Beijing Normal University, Zhuhai, China, 2University of Liverpool, UK, 3University of Southampton, UK, 4Beijing Normal University, China.  
  • Comparative Analysis of Redundancy Schemes for Soft-Error Detection in Low-Cost Space Applications, Charlotte Frenkel, Jean-Didier Legat and David Bol, Universite catholique de Louvain, Belgium.
  • A Novel Soft Error tolerant FPGA Architecture, Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida and Toshinori Sueyoshi, Kumamoto University, Japan.

11:00 - 12:15     Session 4b: Synthesis

Moderator: Peeter Ellervee, Tallinn University of Technology, Estonia 

  • Multi-Function Logic Synthesis of Silicon and Beyond-Silicon Ultra-Low Power Pass-Gate Circuits, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Politecnico di Torino, Italy.
  • Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient Hardware Generators, Wolfgang Ecker and Johannes Schreiner, Infineon Technologies, Germany.
  • Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions, Anna Bernasconi1, Valentina Ciriani2, Luca Frontini2, Gabriella Trucco2, 1Pisa University, Italy, 2Universitá degli Studi di Milano, Italy.

12:15 - 13:30     Lunch

13:30 - 14:45     Session 5a: Reliability and Design-for-Test

Moderator: Ian O'Connor, Lyon Institute of Nanotechnology, France

  • Hybrid TFET-MOSFET Circuits: An Approach to Design Reliable Ultra-Low Power Circuits in the presence of Process Variation, Maedeh Hemmat1, Mehdi Kamal1, Ali Afzali-Kusha1 and Massoud Pedram2, 1University of Tehran, Iran, 2University of Southern California, US.
  • A DFT Scheme for Pneumatic Control Logic in Flow-based Biochips, Seetal Potluri, Paul Pop and Jan Madsen, Technical University of Denmark, Denmark.
  • Online Digital Compensation Method for AMR Sensors, Andreina Zambrano and Hans Kerkhoff, University of Twente, Netherlands.

13:30 - 14:45     Session 5b: Low-Power and Thermal IC Design

Moderator: Kyoung Choi,Seoul National University, Korea

  • Ultra-Fine Grain Vdd-Hopping for Energy-Efficient Multi-Processor SoCs, Valentino Peluso1, Andrea Calimera1, Enrico Macii1 and Massimo Alioto2, 1Politecnico di Torino, Italy, 2National University of Singapore, Singapore.
  • Faster-than-at-speed execution of functional programs: an experimental analysis, Paolo Bernardi1, Alberto Bosio2, Giorgio Di Natale2, Andrea Guerriero1 and Federico Venini1, 1Politecnico di Torino, Italy, 2LIRMM, Université Montpellier, France.
  • A Hybrid Power Estimation Technique to Improve IP Power Models Quality, Alejandro Nocua1, Arnaud Virazel1, Alberto Bosio1, Patrick Girard1 and Cyril Chevalier2, 1LIRMM - CNRS, Université Montpellier, 2STMicroelectronics, France.

14:45 - 15:00    Closing Session

15:00 - 15:30     Farewell Coffee