IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
VLSI-SoC 2016
September 26-28, 2016 Tallinn, ESTONIA


VLSI-SOC 2016 is proud to announce the following keynotes:




"Emerging Trends in Nano-Architectures", Prof. Giovanni De MicheliEPF Lausanne, Switzerland


New electronic devices are game changers for VLSI Systems on Chips. Indeed, new geometries, materials and properties enable both enhanced functionality of silicon devices as well as new opportunities to achieve high performance with low energy consumption. VLSI design systems, leveraging new CAD algorithms, methods and tools are quintessential for exploring the wide spectrum of nano-device configurations as well as choosing the best architectural design. Moreover, such devices can incorporate new sensing modalities as well as providing new interface paradigms.


Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at EPF Lausanne, Switzerland. He is program leader of the Nano-Tera.ch program. Previously, he was Professor of Electrical Engineering at Stanford University.He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983). Prof. De Micheli is a Fellow of ACM and IEEE and a member of the Academia Europaea. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 700 technical articles. His citation h-index is 87 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC (Leuven, B), CfAED (Dresden, D) and STMicroelectronics. Prof. De Micheli is the recipient of the 2016 EDAA Lifetime Achievement Award, of the 2012 IEEE/CAS Mac Van Valkenburg award for contributions to theory, practice and experimentation in design methods and tools and of the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He received also the Golden Jubilee Medal for outstanding contributions to the IEEE CAS Society in 2000, the D. Pederson Award for the best paper on the IEEE Transactions on CAD/ICAS in 1987, and several Best Paper Awards, including DAC (1983 and 1993), DATE (2005) and Nanoarch (2010 and 2012). He has been serving IEEE in several capacities, namely: Division 1 Director (2008-9), co-founder and President Elect of the IEEE Council on EDA (2005-7), President of the IEEE CAS Society (2003), Editor in Chief of the IEEE Transactions on CAD/ICAS (1997-2001). He has been Chair of several conferences, including Memocode (2014) DATE (2010), pHealth (2006), VLSI SOC (2006), DAC (2000) and ICCD (1989).



"From FinFETs to Monolithic 3D Integration"Prof. Niraj K. JhaDept. of Electrical Engineering, Princeton University, USA


The semiconductor industry made a decisive move from CMOS towards FinFETs starting with the 22nm technology node. The industry uses different flavors of FinFETs: double-gate and tri-gate. This move improved performance while lowering leakage power. However, the memory and power walls have not gone away.  Another wall, which we may call the device wall, lurks just ahead. It is uncertain which, if any, device replaces FinFETs in the coming decade.  Possible help in this regard may come from monolithic 3D integration. This may help alleviate the memory and power walls, while pushing the device wall further into the future.  In this talk, we will discuss FinFET variants and their impact at the device, circuit, and architecture levels of the design hierarchy. We will then see how monolithic 3D integration based on FinFET technology provides one way forward.


Niraj K. Jha received his B.Tech. degree in Electronics and Electrical Communication Engineering from Indian Institute of Technology, Kharagpur, India in 1981 and Ph.D. degree in Electrical Engineering from University of Illinois at Urbana-Champaign in 1985. He is a Professor of Electrical Engineering at Princeton University. He also serves as an Associate Director for the Princeton Andlinger Center for Energy and the Environment. He is a Fellow of IEEE and ACM. He received the Distinguished Alumnus Award from IIT, Kharagpur in 2014. He has co-authored or co-edited five books, among which are “Switching and Finite Automata Theory, 3rd ed.” and “Testing of Digital Systems” that are textbooks being used around the world. He has served as the editor-in-chief of IEEE Transactions on VLSI Systems and on the editorial boards of several other IEEE Transactions. He is an author or co-author of more than 400 papers among which are 14 award-winning papers. His research interests include FinFETs, power analysis and optimization, IC design automation, computer architecture, computer security, quantum computing, and energy-efficient buildings.


"From reliability to SoC-level fault management", Dr. Artur JutmanTestonica Lab, Estonia


Semiconductor products manufactured with latest and emerging processes are increasingly prone to wear out and aging. While the fault occurrence rate in such systems increases, the fault tolerance techniques are becoming even more expensive and one cannot rely on them alone. Rapid emergence of embedded instrumentation as an industrial paradigm and adoption of respective IEEE 1687 standard by key players of semiconductor industry opens up new horizons in developing efficient on-line health monitoring frameworks for prognostics and fault management. The talk reviews current challenges and describes a cross-layer framework capable of handling soft and hard faults as well as the system's degradation. In addition to mitigating/correcting the faults, the system may systematically monitor, detect, localize, diagnose and classify them (manage faults). As a result of such fault management approach, the system may continue operating and degrade gracefully even in case if some of the system’s resources become unusable due to intolerable faults. Embedded monitors and sensors as well as Built-In Self-Test (BIST) facilities and various checkers called collectively Embedded Instrumentation form the fundamental layer of the framework and are responsible for collecting service information. An important property of such approach is that the data exchange is done in very rare occasions, based on thresholds or fault detection conditions. As a result, simple mechanisms would allow to disregard the vast majority of irrelevant data. On the top level, the fault management software takes responsibility for proper reaction on interrupts, handling received information and initiating follow-up service actions, e.g. scheduling diagnostic procedures in case of faults, scheduling tasks for re-execution, updating health-map data. The value of the described framework is especially evident for modern high complexity devices and advanced node digital SoCs, which are increasingly prone to defects and wear-out.


Dr. Artur Jutman is the Managing Director of Testonica Lab company. He received a PhD degree from TU Tallinn, Estonia. Since 2005, Dr. Jutman managed R&D projects and services in the field of manufacturing testing, debug and diagnostics in Testonica. His research interests include embedded instrumentation, board/system test, and defect modeling (with over 130 research papers published).
Dr. Jutman has been invited to give two TTEP tutorials (ITC’2015 and LATS’2016) as well as a lecture at ETS’2016 Test Spring School and numerous hands-on training courses and lectures in testing, diagnostics, and DFT for graduate students in Germany, Sweden, Portugal, and Russia. A. Jutman has been a visiting researcher in: TU Darmstadt, TU Ilmenau, University of Linkoping and University of Jonkoping as well as in TU Warsaw.