IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
VLSI-SoC 2016
September 26-28, 2016 Tallinn, ESTONIA

Fringe Workshop RENS 2016

This year VLSI-SoC hosts one fringe workshop.

RENS'16 - 1st International Workshop on Resilience in Nanoelectronic Systems

September 28-29, 2016, Tallinn, Estonia

This tutorial-style workshop delivers a broad overview of the cutting-edge topics in the area of nanoelectronic systems' resilience. These include aging modeling, life-time prediction, error-checking, embedded instruments for system health monitoring, fault management, resilient many-core architectures, design validation/verification and automated debug. The event provides a unique chance to join experts from three on-going European projects as well as researchers working in the area of reliable electronic system design. The workshop is organized by Horizon 2020 Twinning Action TUTORIAL, FP7 STREP BASTION and Horizon 2020 RIA IMMORTAL.

Registration: use VLSI-SOC 2016 Registration webpage


Wednesday, September 28 (room Peterson I, 2nd floor)

15:45 - 16:30 Welcome and Overview Matteo Sonza Reorda, Politecnico di Torino, Italy; Artur Jutman, Testonica Lab, Estonia; Jaan Raik, Tallinn UT, Estonia

16:30 - 18:00 Keynote IC Technology and Computing: The Good, The Bad and The Challenging, Said Hamdioui, Delft UT, Netherlands

18:00 - 18:15 Coffee Break

18:15 - 19:30 Wine and Cheese Panel

Moderator: Artur Jutman, Testonica Lab, Estonia

19:30 - 22:00 Welcome Reception

Thursday, September 29 (room Taamsaare, 7th floor)

9:00 - 9:30 Invited talk Screening Reliability Defects in Emerging Technology Nodes, Victor Champac, INAOE, Mexico

9:30 - 10:30 Embedded tutorial Highly dependable many-core SoCs by lifetime prediction and embedded instrumentation, Hans Kerkhoff, University of Twente, Netherlands; Kim Sunesen, Gerard Rauwerda, Recore Systems, Netherlands 

10:30 - 11:00 Coffee break / Poster session

11:00 - 11:30 Embedded tutorial Advances in checker verification Eli Arbel, Shiri Moran, IBM, Israel; Roderick Bloem, Franz Röck, Graz UT, Austria; Jaan Raik, Ranganathan Hariharan Tallinn UT, Estonia

11:30 - 12:30 Embedded tutorial Stress measurement for burn-in testing, Paolo Bernardi, Politecnico di Torino, Italy

12:30 - 14:00 Lunch

14:00 - 14:30 Invited talk Migrating from circuit level error correction to system level error resilience, Heinrich Theodor Vierhaus, BTU Cottbus-Senftenberg, Germany

14:30 - 15:30 Embedded tutorial Tool Support for Design Understanding Heinz Riener, Jan Malburg, Görschwin Fey German Aerospace Center (DLR) / University of Bremen, Germany

15:30 - 16:00 Coffee break / Poster session (continues)

16:00 - 16:30 Invited talk Angel's Approach to Digital Testing with Decision Diagrams, Raimund Ubar, Tallinn UT, Estonia

16:30 - 16:40 Closing


More details:


On-site registration options available.


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