10th European Test Symposium

Reval Hotel Olümpia, Tallinn, Estonia
May 22-25, 2005


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IST Project REASON WS
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Nov 18, 2017

IST Project REASON Workshop Abstracts


Web-based Learning in Teaching Test

H. –D. WUTTKE, T. VANGELOV
TECHNICAL UNIVERSITY ILMENAU, GERMANY

ABSTRACT:
The paper presents activities realized in the frame of the REASON project to realize Web-based training materials in the field of testing and system on chip design (SoC). After a short description of the main project tasks and a discussion of distance learning basics, the training content of REASON Workpackage 8 (WP8) is characterized. Furthermore, tool exchange activities and plans for a coordination of future work are presented.

As part of these dissemination activities and as a presentation to a broader public, all training tools developed in the REASON WP8 are listed and presented on a database supported WEB page. Chosen examples dealing with the basic types of training tools are treated more explicit during the presentation.



eTools for Teaching and Application of Digital Systems Testability Techniques

M. FISCHEROVÁ, M. BALÁŽ, E. GRAMATOVÁ, T. PIKULA, M. ŠIMLAŠTÍK
INSTITUTE OF INFORMATICS OF THE SLOVAK ACADEMY OF SCIENCES

A contribution will present a set of software tools for teaching and application of design for testability (DfT) and built-in self-test (BIST) techniques for digital circuits and systems that are easily accessible on the Internet.

The developed set includes following tools that are implemented as Java applets:

BIST and MemBIST are aimed to explanation of built-in self-test methods, functionality of each BIST architecture component, as deterministic test pattern generator construction based on linear feedback shift register and cellular automaton, methods of signature compaction and of test response analysis for logic; address generation, fault models and March test algorithm for different fault type detection for memory circuits respectively.

Wrapper explicates usage of a test wrapper that ensures test access - connection to blocks or system embedded cores inaccessible from system ports that is compliant with recommended standard IEEE P1500 SECT (Standard for Embedded Core Test). Besides description of the basic wrapper architecture, the tool explains and demonstrates test access time optimisation techniques for a serial and parallel interface.

The Web-based applet modules simulate the learning subject in a well illustrative graphical form that is self-explanatory, take advantage of learning by doing and involve interaction possibilities. Besides of explicative learning modules, all three tools contain also generation modules for automatic synthesis of testability techniques (BIST or DfT architectures) into a circuit under test modelled in VHDL. The generated high level VHDL hardware hierarchical description of the circuit/system completed by testability architectures of given parameters can be simulated in commercial VHDL simulators (e.g. ModelSim).

The tool set has been utilised in the education process at the Faculty of Informatics and Information Technology of the Slovak University of Technology in Bratislava, subject Digital Systems Testing, but can be used during self-study by designers, as well. Using such web-based tools during laboratory works (some laboratory tasks have been developed based on the presented set) makes the subject more attractive for students and those who are motivated to apply DfT and BIST techniques to real circuits.



Functional test generator at high abstraction level

R.SHEINAUSKAS
KAUNAS UNIVERSITY OF TECHNOLOGY, LITHUANIA

Functional tests are important for design validation, and they potentially have enough high defect coverage independent of the circuit implementation. The functional test set is effective in detecting defects of various types, more than a test set generated for a specific fault model. We introduce a test generator based on test selection by means of simulation at algorithmic level of circuit description on C programming language. The generated test can be applied to VHDL behavioral level as test bench. The test generated has high fault coverage at equivalent gate level. Iterative logic array model allows sequential circuits to consider like combinational ones. Functional test generation approach at high abstraction level is implemented in the test generation program that is available on the internet for free use.



Handbook of Testing Electronic Systems

ONDREJ NOVÁK
TECHNICAL UNIVERSITY OF LIBEREC

The presentation summarizes contributions of the handbook authors. The handbook is focused on testing both of analogue and digital circuits. It differs from other publications about diagnostic problems especially in including practical exercises that can help students to understand the described problems in deep. It contains description of web tools that can be used for the teaching process support.

Shortened content of the book: defects, faults, fault models, test generation techniques and algorithms, design for testability, built-in self-test, on-line testing, Iddq testing, analog test and diagnosis.