Digital Systems Modeling and Synthesis

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Abstract (annotatsioon) Course goals, Study outcomes Prerequisites, Evaluation

Content ( lectures , hands-on exercises ) Exam Curricula

Literature WWW Simulators

Abstract

Modeling concepts for digital and analog hardware. Co-modeling of software and hardware. Hardware description languages - VHDL, SystemVerilog, SystemC - description styles, simulation engines, synthesizability. Digital systems synthesis at different abstraction levels. Simulation and synthesis using modern design tools.

Annotatsioon - Digitaal- ja analoogriistvara modelleerimise alused. Tark- ja riistvara koos-modelleerimine. Riistvara kirjelduskeeled - VHDL, SystemVerilog, SystemC - kirjeldus-stiilid, simulatsiooniskeemid, sünteesitavus. Digitaal-süsteemide süntees erinevatel abstraktsioonitasemetel. Simuleerimine ja süntees tänapäevaste disainivahenditega.

Course goals

• To give overview about phases, methods and tools of modern microchips and embedded systems design process;
• to give thorough overview about digital systems modeling and co-modeling;
• to give thorough overview about hardware description languages VHDL, SystemVerilog and SystemC, and about their features;
• to teach how to use different hardware description languages at various abstraction levels;
• to give overview about synthesis of digital systems at various abstraction levels;
• to give overview about analog systems modeling;
• to teach how to use commercial simulation an synthesis tools;

Eesmärgid:
• Anda ülevaade kaasaegsete mikroskeemide ja sardsüsteemide projekteerimise käigust, meetoditest ja vahenditest;
• anda põhjalik ülevaade digitaalsüsteemide modelleerimisest ja koos-modelleerimisest;
• anda põhjalik ülevaade riistvara kirjelduskeeltest VHDL, SystemVerilog ja SystemC ning nende iseärasustest;
• õpetada erinevate riistvara kirjelduskeelte kasutamist erinevatel abstraktsioonitasemetel;
• anda ülevaade digitaalsüsteemide sünteesist erinevatel abstraktsioonitasemel;
• anda lühiülevaade analoog-süsteemide modelleerimisest;
• õpetada tööstuslike simuleerimis- ja sünteesivahendite kasutamist.

Study outcomes

• Knowledge of phases, methods and tools of modern microchips and embedded systems design process; how to use various hardware description languages at these phases.
• Knowledge how to create models of digital systems in VHDL, SystemVerilog and SystemC, and how to use commercial simulation and synthesis tools.

Õpiväljundid:
• Kaasaegsete mikroskeemide ja sardsüsteemide projekteerimise põhietappide tundmine, oskus kasutada erinevaid riistvara kirjelduskeeli neil etappidel.
• Oskus luua digitaalseadmete mudeleid nii VHDL-s, SystemVerilog-s, kui ka SystemC-s, ning kasutada tööstuslikke simuleerimis- ja sünteesipakette.

Prerequisites

To pass the course successfully, one must have basic knowledge of VHDL and C++ programming. Familiarity with UNIX/Linux environment is a plus for hands-on exercises.

Evaluation

Hands-on exercises - During hands-on exercises, different modeling and synthesis tasks are solved using various tools. The exercises cover the use of various hardware description languages to model digital and analog circuits. The exercises also cover synthesis of digital circuits using different technologies.

Prerequisites for the final exam - Reports of hands-on exercises must be presented and defended before exam.

Exam - On the exam, a student will answer to two questions covering all topics of the course - one question about hardware description languages and one about synthesis related issues.

Content

1.  Lectures
2.  Hands-on exercises
3.  Exam -- Requirement - lab reports accepted before the examination day.

Curricula

• Digital systems design - design-flow, automation.
• Simulation of digital systems, simulation engines.
• High-level synthesis - subtasks, examples.
• Hardware description language SystemC.
• Hardware description language SystemVerilog.
• Co-modeling and co-simulation of digital systems.
• VHDL and register-transfer level synthesis.
• Synthesis of digital systems at various abstraction levels.
• Modeling of analog and mixed signal systems - SPICE, VHDL-AMS.
• Code transformations at system and algorithmic levels.
• System level description languages.

Everything below this will be updated in coming days...

Literature

There are many-many books available and the list below is only a brief overview. In principle, one book about one of the languages is enough - the main differences are in syntax. Except maybe that SystemC has more differences...

In TUT library

NB! These are only some of the books at the library.

• Michael John Sebastian Smith. Application-Specific Integrated Circuits. Addison-Wesley, ptk. 10,11 [1997]
• Dirk Jansen et al. (editors). The electronic design automation handbook. Kluwer Academic Publishers, ptk. 4,10-13 [2003]

• Zainalabedin Navabi. Digital system test and testable design: using HDL models and architectures. Springer [2012]

• K.C. Chang. Digital systems design with VHDL and synthesis: an integrated approach. IEEE Computer Society [1999]
• Ben Cohen. VHDL coding styles and methodologies: [... an in-depth tutorial]. Kluwer [1995]
• Stefan Sjoholm and Lennart Lindh. VHDL for designers. Prentice Hall [1997]
• David Pellerin, Douglas Taylor. VHDL made easy. Prentice Hall [1997]
• Kalle Tammemäe. Riistvara kirjeldamiskeel VHDL: metoodiline materjal. Tallinna Tehnikaülikool [2002]

• Ken Coffman. Real world FPGA design with Verilog. Prentice Hall [2000]
• Donald E. Thomas and Philip R. Moorby. The Verilog hardware description language. Kluwer [1996]

• David C. Black, Jack Donovan. SystemC: From the Ground Up. Springer, [2004]

Additional literature

• K.Tammemäe. Riistvara kirjeldamiskeel VHDL. TTÜ toimetus, 1992.   
• K.Tammemäe. Riistvara simuleerimisvahend - VHDL. Avutustehnika & Andmetöötlus (A&A), 4/1992.
• K.Tammemäe. VLSI kõrgtaseme süntees. A&A, 1/1993.
• K.Tammemäe. VHDL täna ja homme. A&A, 9/1993.
• K.Tammemäe. Kas VHDL on sobiv keel sünteesiks. A&A, 7-8/1995.
• P. Ellervee. Riistvara kirjelduskeel Verilog. A&A, 1/1998.

• П. Н. Бибило (P.N.Bibilo). Основы VHDL языка (Osnovy VHDL jazyka). Солон-Р (Solon-R), 2000, ISBN 5-93455-056-X.

• Stuart Sutherland, Simon Davidmann, Peter Flake and Phil Moorby. SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling. Springer
• James M. Lee. Verilog Quickstart: a practical guide to simulation and synthesis in Verilog. Kluwer

• Thorsten Grötker, Stan Liao, Grant Martin, Stuart Swan. System Design with SystemC. Springer, 2002, ISBN 1-4020-7072-1

Plus newer editions of the same books, of course.

WWW

There exist hundreds of web-pages. Some to start with are below.

• VHDL Analysis and Standardization Group
• comp.lang.vhdl FAQ

• Peter J. Ashenden - The Student's Guide to VHDL & The Designer's Guide to VHDL
• Robert Reese - Course notes on Logic Design Course with VHDL & Course notes on Modeling with VHDL

• SystemVerilog.in
• Project Veripage
• Alternate Verilog FAQ
• Verilog Resources

• SystemC Community

Simulator & synthesizer at home

• ModelSim PE Student Edition (Model Technology) - HDL simulator for students (limited design size but enough for term projects, Internet connection required to get license, only for MS Windows).
• WebPACK (Xilinx) - tools to simulate and synthesize smaller designs (MS Windows & Linux-s).
• GHDL and gtkWave - simulator and waveform viewer (MS Windows, Linux-s, etc., GPL - freeware & open-source).
• Active-VHDL Simulation design environment (30-day trial license).

Last modified 2018.05.18.