Compendium #2: Shift Registers

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General Instruction
*** There will be a test based on this compendium at the start of lab session on 25th September 2014.
*Students who fail the test will need to submit a handwritten solution to the compendium before they can start the lab work. They also need to pass an oral examination of the compendium.

Introduction

The motivation for introducing the compendiums for the student to be prepared with the relevant concepts before entering the exercise session. Students are excepted to know the following concepts.

  1. Important Concepts

    :

    1. What are flip flops, registers and latches? how do we avoid latches?

    2. What are what are counters and shift registers?

    3. How to make a register or a wire with a signal and VHDL?

    4. What is debouncing? How to use buttons on FPGA board and mitigate debouncing?

  2. Exercise Questions

    1. Fill the correct diagrams and Codes in the table
      2. DiagramCode
      Dflipflop with asynchronous negetive Reset to 1 Figure(_________)Code(_________)
      Dflipflop with asynchronous negetive Reset to 0 Figure(_________)Code(_________)
      Dflipflop with asynchronous postive Reset to 1 Figure(_________)Code(_________)
      Dflipflop with asynchronous postive Reset to 0 Figure(_________)Code(_________)
      Dflipflop with synchronous negetive Reset to 0 Figure(_________)Code(_________)
      Dflipflop with synchronous positive Reset to 0 Figure(_________)Code(_________)
      Dflipflop with synchronous negetive Reset to 0 Figure(_________)Code(_________)
      Dflipflop with synchronous positive Reset to 0 Figure(_________)Code(_________)
      1. Code(1) 
        	signal d,clk,q,reset :std_logic; 
	process(clk,d)
	begin 
		if (clk’event and clk=’1’) then
			if reset = '1' then
				q <= '0';					
			else 			
				q <= d;
			end if;
		end if; 
	end process;
      2. Code (2) 
        	signal d,clk,q,reset :std_logic; 
	process(clk,d)
	begin 
		if (clk’event and clk=’1’) then
			if reset = '1' then
				q <= '1';					
			else 			
				q <= d;
			end if;
		end if; 
	end process;
      3. Code (3) 

        	signal d,clk,q,reset :std_logic; 
	process(clk,d)
	begin 
		if (clk’event and clk=’1’) then
			if reset = '0' then
				q <= '0';					
			else 			
				q <= d;
			end if;
		end if; 
	end process;

      4. Code (4) 

        	signal d,clk,q,reset :std_logic; 
	process(clk,d)
	begin 
		if (clk’event and clk=’1’) then
			if reset = '0' then
				q <= '1';					
			else 			
				q <= d;
			end if;
		end if; 
	end process;

      5. Code (5) 

        	signal d,clk,q,reset :std_logic; 
	process(clk,d)
	begin 
		if reset = '1' then
			q <= '0';					
		elsif (clk’event and clk=’1’) then
			q <= d;
		end if; 
	end process;

      6. Code (6) 

        	signal d,clk,q,reset :std_logic; 
	process(clk,d)
	begin 
		if reset = '1' then
			q <='1';			
		elsif (clk’event and clk=’1’) then
			q <= d;
		end if; 
	end process;

      7. Code (7) 

        	signal d,clk,q,reset :std_logic; 
	process(clk,d)
	begin 
		if reset = '0' then
			q <='0';					
		elsif (clk’event and clk=’1’) then
			q <= d;
		end if; 
	end process;

      8. Code (8) 

        	signal d,clk,q,reset :std_logic; 
	process(clk,d)
	begin 
		if reset = '0' then
			q <= '1';					
		elsif (clk’event and clk=’1’) then
			q <= d;
		end if; 
	end process;
    2. Which of the following codes result in latch,register or a combinational circuit? Also Describe what is the resulting design.
      ### REGISTER WITH COMBINATIONAL CIRCUIT LATCH WITH COMBINATIONAL CIRCUIT ONLY COMBINATIONAL CIRCUIT Description of the resulting design
      Code 1 yes(_____)/No(_____) yes(_____)/No(_____) yes(_____)/No(_____)
      Code 2 yes(_____)/No(_____) yes(_____)/No(_____) yes(_____)/No(_____)
      Code 3 yes(_____)/No(_____) yes(_____)/No(_____) yes(_____)/No(_____)
      Code 4 yes(_____)/No(_____) yes(_____)/No(_____) yes(_____)/No(_____)
      Code 5 yes(_____)/No(_____) yes(_____)/No(_____) yes(_____)/No(_____)
      Code 6 yes(_____)/No(_____) yes(_____)/No(_____) yes(_____)/No(_____)
      1. Code 1 

        	signal c,a,b,select,clk :std_logic; 
	process(clk,a,b,select)
	begin 
		if (clk’event and clk=’1’) then
			if select = '1' then
				c <= a and b;
			else 			
				c <= a or b;
			end if;
		end if; 
	end process;
      2. Code 2 

        	signal c,a,b,select,clk :std_logic; 
	process(clk,a,b,select)
	begin 
		if (clk’event and clk=’1’) then
			if select = '1' then
				c <= a and b;
			end if;
		end if; 
	end process;
      3. Code 3 

        	signal c,a,b,select :std_logic; 
	process(a,b,select)
	begin 
		if select = '1' then
			c <= a and b;
		end if;
	end process;
      4. Code 4 

        	signal c,a,b,clk :std_logic; 
	process(clk,a,b)
	begin 
		if (clk=’1’) then
			c <= a and b;
		end if; 
	end process;
      5. Code 5 

        	signal c,a,b,clk :std_logic; 
	process(clk,a,b)
	begin 
		c <= a or b; 
		if (clk=’1’) then
			c <= a and b;
		end if; 
	end process;
      6. Code 6 

        	signal c,a,b,clk :std_logic; 
	process(clk,a,b)
	begin 
		if (clk=’1’) then
			c <= a and b;
		else 			
			c <= a or b;
		end if;
	end process;
    3. Which of the following codes result Shift register?
      -- Shift Register Description the design
      Code 1 yes(_____)/No(_____)-
      Code 2 yes(_____)/No(_____)-
      Code 3 yes(_____)/No(_____)-
      Code 4 yes(_____)/No(_____)-

      1. Code 1 

        	signal s0,s1,s2,s3,clk :std_logic; 
	process(clk,s1,s2,s0)
	begin 
		if (clk’event and clk=’1’) then
			s1 <= s0;
			s2 <= s1;
			s3 <= s2;
		end if; 
	end process;
      2. Code 2 

        	signal clk :std_logic; 
	process(clk,s1,s2,s0)
	variable s0,s1,s2,s3 :std_logic;
	begin 
		if (clk’event and clk=’1’) then
			s1 := s0;
			s2 := s1;
			s3 := s2;
		end if; 
	end process;
      3. Code 3 

        	signal clk :std_logic; 
	process(clk,s1,s2,s0)
	variable s0,s1,s2,s3 :std_logic;
	begin 
		if (clk’event and clk=’1’) then
			s3 := s2;
			s2 := s1;
			s1 := s0;
		end if; 
	end process;
      4. Code 4 

        	signal s0,s1,s2,s3 :std_logic; 
	process(S0,s1,s2)
	begin 
		s1 <= s0;
		s2 <= s1;
		s3 <= s2;
	end process;