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Welcome to RecoSoC 2016!

Over the past decade ReCoSoC has established itself as a international reference event for research in the areas of reconfigurable and communication-centric systems-on-chip. Its informal and dynamic philosophy encourages technical and scientific interactions of both academic and industrial participants through presentations and special sessions reporting latest advances in the related areas.

ReCoSoC 2016 will be held in Tallinn, ESTONIA at Nordic Hotel Forum.


Program

 

Monday

June 27

9:00

Registration

9:30

Opening

9:45

Keynote - Jan Madsen

10:45

Coffe Break

Session 1 - Network-on-Chip. Session Chair: Jaan Raik

11:15

Miltos D. Grammatikakis, Kyprianos Papadimitriou, Polydoros Petrakis, Michael Soulie and Marcello Coppola. Address Interleaving for Low-cost NoCs

11:45

Manuel Selva, Abdoulaye Gamatie, David Novo and Gilles Sassatelli. Speed and Accuracy Dilemma in NoC Simulation: What about Memory Impact?

12:15

Tripti Jain, Klaus Schneider and Anoop Bhagyanath. The Selector-Tree Network: A New Self-Routing and Nonblocking Interconnection Network

12:45

Lunch

Session 2 - Special Session: Emerging Technologies for Reconfigurable Systems in the Manycore Era. Session Chair: Davide Patti

14:00

Luca Pezzarossa, Martin Schoeberl and Jens Sparsø. Reconfiguration in FPGA-Based Multi-Core Platforms for Hard Real-Time Applications

14:30

Dirk Stroobandt, et.al. Towards the Exploitation of Exascale Technology for Reconfigurable Architectures

15:00

David Andrews and Marco Platzner. Programming Models for Reconfigurable Manycore Systems

15:30

Coffee + posters

16:00

Invited Talk - Eduardo de La Torre

16:45

Panel - Embedded, high performance, cloud: is there a common design approach?. Organizer: Leandro Soares Indrusiak

18:00

End

19:30

Welcome reception



   

Tuesday

June 28

 Session 3 - Special Session: Secure multi/many-core architectures in the era of Internet-of-Things. Session Chair: Johanna Sepulveda

9:30

Martha Johanna Sepulveda, Daniel Florez, Guy Gogniat, Ramon Fernandes, Cesar Marcon and Georg Sigl. Towards Risk Aware NoCs for Data Protection in MPSoCs

10:00

Teng Xu, Hongxiang Gu and Miodrag Potkonjak. An Ultra-Low Energy PUF Matching Security Platform Using Programmable Delay Lines

10:30

Maria Méndez Real, Vincent Migliore, Vianney Lapotre, Guy Gogniat, Philipp Wehner and Diana Göhringer. Dynamic Spatially Isolated Secure Zones for NoC-based Many-core Accelerators

10:45

Muhammad Rashid, Malik Imran and Atif Raza Jafri. Comparative Analysis of Flexible Cryptographic Implementations

11:00

Coffee

Session 4 - Mixed-Criticality. Session Chair: Dirk Stroobandt

11:15

George Tsamis, Stamatis Kavvadias, Antonis Papagrigoriou, Miltos Grammatikakis and Kyprianos Papadimitriou. Efficient Bandwidth Regulation at Memory Controller for Mixed Criticality Applications

11:45

Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan and Thomas Hollstein. SoCDep²: A framework for dependable task deployment on many-core systems under mixed-criticality constraints

12:00

Othon Tomoutzoglou, Dimitrios Mbakoyannis, Georgios Kornaros and Marcello Coppola. Efficient Communication in Heterogeneous SoCs with Unified Address Space

12:15

Lunch

Session 5 - Reliability. Session Chair: Kyprianos Papadimitriou

13:15

Poona Bahrebar and Dirk Stroobandt. Online Reconfigurable Routing Method for Handling Link Failures in NoC-based MPSoCs

13:45

Elham Kashefi, Hamid R. Zarandi and Ann Gordon-Ross. Postponing Wearout Failures in Chip Multiprocessors Using Thermal Management and Thread Migration

14:15

Luca Sterpone, Luca Boragno and David Merodio Codinachs. Analysis of Radiation-Induced SEUs on Dynamic Reconfigurable Systems

14:30

Coffee + posters

15:00

End

15:15

Social Event





Wednesday

June 29

9:30

Invited Talk - Artur Jutman

Session 6 - System Design for Heterogeneous 3D-Architectures. Session Chair: Thilo Piontheck

10:15

Jan Moritz Joseph, Sven Wrieden, Christopher Blochwitz, Alberto Garcia-Oritz and Thilo Pionteck. A Simulation Environment for Design Space Exploration for Asymmetric 3D-Network-on-Chip

10:45

Wolfgang Büter, Dominic Oehlert and Alberto Garcia-Ortiz. ERRCA: A buffer-efficient reconfigurable optical Network-on-Chip with permanent-error recognition

11:00

Coffee

Session 7 - Reconfigurable Computing. Session Chair: Peeter Ellervee

11:15

Tobias Wiersema and Marco Platzner. Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware

11:45

William Harrison, Ian Graves, Adam Procter, Michela Becchi and Gerard Allwein. A Programming Model for Reconfigurable Computing Based in Functional Concurrency

12:15

Ayad Dalloo and Alberto Garcia-Ortiz. A Programmable and Reconfigurable Core for Binary Image Processing

12:30

Snacks + Posters + Closing

13:00

End