Monday, June 27th 2016
„The Future of Advanced Microsystems"
Abstract: With embedded systems, we have focused on making things in our environment smart, by integrating computing power into them. With the introduction of Cyber-Physical Systems (CPS), we have emphasised the interaction of the computing system with its physical environment. However, as other technologies get digitised and miniaturised, we are able to integrate part of the physical environment into our computing devices.
This talk will outline the trends and challenges of integrating microfluidic biochips with our computing devices. Microfluidic biochips are replacing the conventional biochemical analysers, and are able to integrate on-chip all the necessary functions for biochemical analysis at the micro scale. At this scale it is possible to study and manipulate living cells, and even re-program the behaviour of living cells by systematically changing parts of their DNA, effectively implementing biological logic functions.
Bio: Jan Madsen is Full Professor in Computer-Based Systems at Department of Applied Mathematics and Computer Science (DTU Compute), at the Technical University of Denmark (DTU). He is Head of the Section of Embedded Systems Engineering and is co-Director of DTU Compute. He is national ICT expert for EU Horizon2020 and member of the NTF evaluation panel for Nano-Tera, a Swiss Research Program on engineering complex systems since 2013. His main research interests are related to methods and tools for systems engineering of microelectronic, microfluidic and microbiological computing systems. Present research covers embedded systems-on-a-chip, wireless sensor networks (Internet-of-Things), microfluidic labs-on-a-chip and synthetic biology.
He has published more than 150 peer-reviewed conference and journal papers, 12 book chapters, and 3 books. He has several best paper awards and nominations. He is General Chair for DATE 2018 and Vice-General Chair for DATE 2017. He has been General Chair for CODES 2001 and NOCS 2012, Program Chair for NORCHIP 2012, CODES+ISSS 2011, DATE 2007, and CODES 2000. He is a senior member of IEEE Computer Society, has served on the editorial board of IEEE Design & Test 2007-2015 and IET Proceedings of Computers and Digital Techniques 2005-2008. He has served on the technical program committee of numerous conferences. He has 1 pending patent in microfluidics and holds 2 patents on a bio-inspired self-healing computer architecture from which he has co-founded the start-up company, Biomicore.
Eduardo de La Torre
"Hardware Adaptation by Means of DPR: How and What For?"
Abstract: Performance of HW systems may easily outperform that of SW-based systems, except for one thing: flexibility. Although HW reconfiguration is, in essence, as simple as SW reconfiguration (to write new contents in the configuration memory), system adaptation and, more in particular, self-adaptation and other self-* features, such as self-reconfiguration, self-calibration, self-protection, self-awareness or even self-repair, need to be justified and carefully implemented.
This talk provides an overview on the benefits of using FPGA-based reconfigurable systems which may contribute to higher adaptiveness and smartness. Later, a classification of autonomy levels is presented. In the second part of the talk, two example systems are presented. First, a reconfigurable architecture to at runtime trade between performance, fault tolerance and energy consumption is shown, demonstrating how systems may adapt to changing execution conditions. Second, an efficient evolvable hardware system, showing higher levels of functional adaptation and self-healing from faults, is presented.
Bio: Eduardo de la Torre is Associate Professor in Electronics at the Technical University of Madrid, doing his research at the Centre of Industrial Electronics. He obtained his PhD in Electrical Engineering from UPM in 2000. His main expertise is in FPGA design, embedded systems design, signal processing and partial and dynamic reconfiguration of digital systems. He has participated in nine EU funded projects and, overall, in six funded projects related with reconfigurable systems.
He has more than 40 papers on reconfigurable systems in the last five years, and he has been Program Co-Chair of conferences such as Reconfig, DASIP, DCIS and ReCoSoc, as well as track coordinator or PC-member of other reconfiguration-related conferences such as FPL, RAW, WRC, LP-EMS or ISVLSI. He has also been guest editor in Journals such as the Journal on Microprocessors and Microsystems, Computers and Electrical Engineering, Eurasip Jorunal on Advances in Signal Processing.
Wednesday, June 29th 2016
"Managing Faults in Many-Core Systems During Operation"
Abstract: Semiconductor products manufactured with the latest and emerging processes are increasingly prone to wear out and aging. While the fault occurrence rate in such systems increases, the fault tolerance techniques are becoming more expensive and less effective. Rapid emergence of embedded instrumentation as an industrial paradigm and adoption of respective IEEE 1687 standard by key players of semiconductor industry opens up new horizons in developing efficient on-line health monitoring frameworks for prognostics and fault management. The talk reviews current challenges and describes a cross-layer framework capable of handling soft and hard faults as well as the system's degradation. In addition to mitigating/correcting the faults, the system may systematically monitor, detect, localize, diagnose and classify them (manage faults) supporting continuous operation and graceful degradation even in case of intolerable faults. Embedded monitors, sensors and various checkers called collectively Embedded Instrumentation form the fundamental layer of the framework and are responsible for collecting system health information. Simple threshold-based mechanisms are deployed allowing to disregard the vast majority of irrelevant data. On the top level, the fault management software takes responsibility for proper reaction on interrupts, handling received information and initiating follow-up service actions, e.g. scheduling diagnostic procedures in case of faults, scheduling tasks for re-execution, updating health-map data. The value of the described framework is especially evident for modern high complexity devices and advanced node digital SoCs, which are increasingly prone to defects and wear-out.
Bio: Dr. Artur Jutman is the Managing Director of Testonica Lab. He received a PhD degree from TU Tallinn, Estonia in 2004. He has been a visiting researcher in: TU Darmstadt, TU Ilmenau, University of Linkoping and University of Jonkoping as well as in TU Warsaw. Since 2005, Dr. Jutman managed R&D projects and services in the field of manufacturing testing, debug and diagnostics in Testonica. His research interests include embedded instrumentation, board/system test, and defect modeling (with over 130 research papers published).
Dr. Jutman is a member of Nordic Test Forum executive committee. He has been involved in organizing several workshops and conferences and has been invited to give lectures and embedded tutorials at several conferences as well as two TTEP tutorials (ITC'2015 and LATS'2016). He has been a guest lecturer in several universities of Germany, Sweden, Portugal, and Russia.