module lab1(
	input [7:0] operand_a,
	input [7:0] operand_b,
	input [7:0] operand_c,
	input use_a,
	input use_b,
	input use_c,
	input opcode_add,
	input opcode_sub,
	input opcode_ats, // add then sub
	output reg [7:0] result
);

// if you need temp variables, they are declared here

always @(*) begin
	// your logic goes here
end

endmodule