module lab2 # (
	parameter PKT_WIDTH = 96,
	localparam PKT_WIDTH_M1 = PKT_WIDTH - 1,
	parameter DATA_WIDTH = 32,
	localparam DATA_WIDTH_M1 = DATA_WIDTH - 1
)(
	input clk,
	input [DATA_WIDTH_M1:0] data_i,
	input valid_i,
	output reg [DATA_WIDTH_M1:0] data_o,
	output reg valid_o
);

reg [PKT_WIDTH_M1:0] mypkt;
// pkt format is              |tail |source_id|destination_id|hops|data|header|
// lengths of each field are  |  3  |    10   |      10      |  6 | 64 |   3  |   
// total length is 96

reg [2:0] counter;

always @(posedge clk) begin
	if (valid_i || valid_o) begin
		counter <= counter + 1;
	end
	else begin	
		counter <= 0;
	end
end

always @(posedge clk) begin
	// your logic goes here
end

endmodule