module lab5_tb();

reg clk;
reg rst_n;
reg ld;
reg [19:0] key;
reg [49:0] plaintext;
wire [49:0] ciphertext;
wire done;

lab5 lab5 (
	.clk (clk),
	.rst_n (rst_n),
	.ld (ld),
	.key (key),
	.plaintext (plaintext),
	.ciphertext (ciphertext),
	.done (done)
);

initial begin
        clk = 0;
        rst_n = 0;
        ld = 0;
        key = 20'd0;
        plaintext = 50'd0;
end

always begin
        clk = !clk;
        #5;
end

initial begin
	@(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        rst_n = 1;
        @(negedge clk);
        @(negedge clk);

        ld = 1;
        plaintext = 50'b00001_00001_00001_00001_00001_00001_00001_00001_00001_00001;
        key = 20'b00000_00000_00000_00001; // this is a very simple case to help you debug
	// the expected output is h0421084210842

 	 @(negedge clk);
        ld = 0;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
	ld = 1;
        plaintext = 50'b10001_10001_10001_10001_10001_10001_10001_10001_10001_10001;
        key = 20'b01000_00100_00010_00001; 
	// the expected output is h25294a5294a52
	@(negedge clk);
	ld = 0;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);

        @(negedge clk);
	ld = 1;
        plaintext = 50'd12345;
        key = 20'd12345; 
	// the expected output is h339ce739c9752
	@(negedge clk);
	ld = 0;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);

	$finish();
end


endmodule