module lab2 # (
	parameter PKT_WIDTH = 96,
	localparam PKT_WIDTH_M1 = PKT_WIDTH - 1,
	parameter DATA_WIDTH = 32,
	localparam DATA_WIDTH_M1 = DATA_WIDTH - 1
)(
	input clk,
	input [DATA_WIDTH_M1:0] data_i,
	input valid_i,
	output reg [DATA_WIDTH_M1:0] data_o,
	output reg valid_o
);

reg [PKT_WIDTH_M1:0] mypkt;
// pkt format is              |tail|source_id|destination_id|hops|data|header|
// lengths of each field are  |  3 |    10   |      10      |  6 | 64 |  3   |   
// total length is 96

reg [2:0] counter;

always @(posedge clk) begin
	// your sequential logic goes here
	if (valid_i || valid_o) begin
		counter <= counter + 1;
	end
	else begin	
		counter <= 0;
	end
end

always @(posedge clk) begin
	if (counter == 0) begin	// do nothing
		mypkt <= 96'd0;
		valid_o <= 1'b0;
		data_o <= 32'd0;
	end
	else if (counter == 1) begin
		mypkt[31:0] <= data_i;
		valid_o <= 1'b0;
		data_o <= 32'd0;
	end
	else if (counter == 2) begin
		mypkt[63:32] <= data_i;
		valid_o <= 1'b0;
		data_o <= 32'd0;
	end
	else if (counter == 3) begin
		mypkt[95:64] <= data_i;
		valid_o <= 1'b1;
		data_o <= 32'd0;
	end
	else if (counter == 4) begin
		valid_o <= 1'b1;
		data_o <= mypkt[31:0];
	end
	else if (counter == 5) begin
		valid_o <= 1'b1;
		data_o <= mypkt[63:32];
	end
	else if (counter == 6) begin
		valid_o <= 1'b1;
		data_o <= mypkt[95:64];
	end
	else if (counter == 7) begin
		mypkt <= 96'd0;
		valid_o <= 1'b0;
		data_o <= 32'd0;
	end
end

endmodule