module lab1_tb();

// one reg type var for each input of the circuit
reg [7:0] operand_a, operand_b, operand_c;
reg use_a, use_b, use_c;
reg opcode_add, opcode_sub, opcode_ats;

// one wire type var for the output
wire [7:0] result;

lab1 lab1 (
	.operand_a (operand_a), 
	.operand_b (operand_b), 
	.operand_c (operand_c), 
	.use_a (use_a),
	.use_b (use_b),
	.use_c (use_c),
	.opcode_add (opcode_add),
	.opcode_sub (opcode_sub),
	.opcode_ats (opcode_ats),
	.result (result)
);

initial begin
	operand_a = 8'd0;
	operand_b = 8'd0;
	operand_c = 8'd0;
	use_a = 1'b0;
	use_b = 1'b0;
	use_c = 1'b0;
	opcode_add = 1'b0;
	opcode_sub = 1'b0;
	opcode_ats = 1'b0;
	
	#100; 
	// this will add a and b
	operand_a = 8'd11;
	operand_b = 8'd22;
	operand_c = 8'd99;
	use_a = 1'b1;
	use_b = 1'b1;
	use_c = 1'b0;
	opcode_add = 1'b1;
	opcode_sub = 1'b0;
	opcode_ats = 1'b0;
	
	#100; 
	// this will add b and c
	operand_a = 8'd11;
	operand_b = 8'd22;
	operand_c = 8'd99;
	use_a = 1'b0;
	use_b = 1'b1;
	use_c = 1'b1;
	opcode_add = 1'b1;
	opcode_sub = 1'b0;
	opcode_ats = 1'b0;
	
	#100; 
	// this will subtract: result = a - b = 22 - 12 = 10
	operand_a = 8'd22;
	operand_b = 8'd12;
	operand_c = 8'd99;
	use_a = 1'b1;
	use_b = 1'b1;
	use_c = 1'b0;
	opcode_add = 1'b0;
	opcode_sub = 1'b1;
	opcode_ats = 1'b0;
	
	#100; 
	// this will perform result = a + b - c = 22 + 12 - 3 = 31
	operand_a = 8'd22;
	operand_b = 8'd12;
	operand_c = 8'd3;
	use_a = 1'b1;
	use_b = 1'b1;
	use_c = 1'b1;
	opcode_add = 1'b1;
	opcode_sub = 1'b1;
	opcode_ats = 1'b1;
	
	#100; 
	// would this work? number of operands does not match
	operand_a = 8'd22;
	operand_b = 8'd12;
	operand_c = 8'd3;
	use_a = 1'b1;
	use_b = 1'b1;
	use_c = 1'b1;
	opcode_add = 1'b0;
	opcode_sub = 1'b1;
	opcode_ats = 1'b1;
	
	#100; 
	// would this work? number of operands does not match
	operand_a = 8'd11;
	operand_b = 8'd22;
	operand_c = 8'd99;
	use_a = 1'b0;
	use_b = 1'b0;
	use_c = 1'b1;
	opcode_add = 1'b1;
	opcode_sub = 1'b0;
	opcode_ats = 1'b0;
end

endmodule