module sample (clk, rst_n, a, b, c, s);
input clk;
input rst_n;
input a, b, c;
output reg s;

localparam START = 3'b000;
localparam RUN = 3'b001;
localparam WAIT_A = 3'b010;
localparam WAIT_B = 3'b011;
localparam IDLE = 3'b100;

reg [2:0] state, next_state;
reg [5:0] counter, next_counter;

// this initial block is only here so we can see something on the terminal without a testbench
// (at this point we haven't discussed what a testbench is)
// this is not a good coding practice, one should not mix design and testbench
initial begin
	$display("IAS0630 SAMPLE");
	$display("IAS0630 SAMPLE");
	$display("IAS0630 SAMPLE");
	$display("IAS0630 SAMPLE");
	$display("IAS0630 SAMPLE");
	force clk = 0;
	force rst_n = 0;
	#20;
	force rst_n = 1;
	#1000 $finish();
end

always begin
	#10;
	force clk = 1;
	#10;
	force clk = 0;
end

// from here onwards, the code is normal RTL
always @(posedge clk) begin // sequential logic
	if (rst_n == 1'b0) begin // neg edge rst, synchronous
		state <= START;
		counter <= 6'b100000; // 32 in decimal
	end
	else begin
		state <= next_state;
		counter <= next_counter;
	end
end

always @(*) begin // combinational logic for next_state
	next_state = state; // by default, stays on the same state
	next_counter = counter;

	case (state)
		START: begin 
			next_state = RUN;
		end
		RUN: begin
			if (counter == 0) begin
				next_state = WAIT_A;
			end
			else begin
				next_counter = counter - 1;
			end
		end
		WAIT_A: begin
			if (a) begin
				next_state = WAIT_B;
			end
			else if (c) begin
				next_state = RUN;
			end
		end
		WAIT_B: begin
			if (b) begin
				next_state = IDLE;
			end
			else if (c) begin
				next_state = RUN;
			end
		end
		IDLE: begin 
			next_state = state; 
		end
	endcase
end

always @(*) begin // combinational logic for output
	s = 1'b0;
	case (state)
		IDLE: begin
			s = 1'b1;
		end	
	endcase	
end

endmodule