CDS TT - Revision history

Hardi.selg: /* Libraries for importing to TT */

2016-06-08T15:22:39Z

‎Libraries for importing to TT

Hardi.selg: /* Libraries for importing to TT */

2016-06-08T15:18:46Z

‎Libraries for importing to TT

Hardi.selg: /* Libraries for importing to TT */

2016-06-08T14:56:30Z

‎Libraries for importing to TT

Hardi.selg at 14:55, 8 June 2016

2016-06-08T14:55:41Z

Hardi.selg at 14:24, 8 June 2016

2016-06-08T14:24:05Z

Hardi.selg at 14:21, 8 June 2016

2016-06-08T14:21:00Z

Hardi.selg: Created page with "Purpose of this tutorial is how to export edif out of Cadence Virtuoso
NB! To first import your design into Virtuoso, use this tutorial. __TOC_..."

2016-06-08T09:50:21Z

Created page with "<big>Purpose of this tutorial is how to export edif out of Cadence Virtuoso</big> <br /> <big>NB!</big> To first import your design into Virtuoso, use this tutorial. __TOC_..."

New page

<big>Purpose of this tutorial is how to export edif out of Cadence Virtuoso</big>
<br />

<big>NB!</big>
To first import your design into Virtuoso, use this tutorial.

__TOC__
==Setting up the environment==
''following commands are all in commandline''

:* move to your design folder '''noc_synth'''
:* I have a separate folder for virtuoso, to keep folder structure more clear.
:* using command ''''''cad'''''', choose option ''''1'''' to initialize environment variables for Cadence tools.

::[[File:env_setup.png|Setting up working environment]]

==Bringing up Virtuoso==
:* If you have never invoked following command in your current design folder, then there is a great possibility that you have not imported your design yet and you should follow this tutorial first.
:: <pre>ams_cds -64 -tech c18a6 -add CORELIB -add IOLIB_6AM -add GATES_ANA</pre>
:* If you are sure that you have invoked previously that command and you have design imported, you can bring up Virtuoso with following command.
:: <pre>ams_cds</pre>

==Exporting edif==
For exporting previously imported design we need to only use this window.
::[[File:Virtuoso_main.png|Main Virtuoso window]]

From that window search under ''''''File'''''' menu ''''export'''' and click ''''EDIF200''''
::[[File:export_edif.png|Exporting EDIF]]

This should bring up a following window
::[[File:export_edif_1.png|EDIF export window]]
First step is to ''''Browse'''' for your design.

::[[File:export_edif_browse.png|EDIF export window]]
Find your design by selecting your designs ''''Library'''', then a ''''cell'''' that you want to export and finally ''''schematic''''.
Close the window just by clicking ''''Close'''' and your design should be included now in the '''Export''' window.

::[[File:export_edif_2.png|Setting EDIF export options]]
Final steps before exporting:
:* Set '''External Library''' to ''''CORELIB''''
:* Give your design a name by filling ''' Design Name'''
:* Give '''Output File''' name
:* Set '''Output format''' to ''''Netlist''''
:* Select ''''Expand All Objects Except Ports''''
:* Set '''Netlist Transition Mode''' to ''''Flat''''

When these options have been set, you can push '''OK''' to export your design in edif.

<big>NB!</big>
After Clicking '''OK''' there should appear a prompt for displaying the export log.
Check it to make sure that ''''''Writing cell cds_thru'''''' is '''NOT''' present there.
If it is, then you should re-visit importing your design.
This line generates ''''INOUT'''' ports in the EDIF and TT cannot understand them.

@@ Line 61: / Line 61: @@
 This library also contains D-FlipFlop (DFCX1), which was added because of LBDR.
+This library can be found in our local network under '''/cad/tt/lib''' folder named as '''ams_4.11.lib'''.
-<big>'''Generated TT import library'''</big>
-−
-This library has been generated by a parser script from the '''CORELIB_TYP.lib''' file. This contains all combinational AMS elements, however they have hot yet been verified.
-This version does not include any FlipFlops.

@@ Line 61: / Line 61: @@
 This library also contains D-FlipFlop (DFCX1), which was added because of LBDR.
 <big>'''Generated TT import library'''</big>
@@ Line 67: / Line 66: @@
 This library has been generated by a parser script from the '''CORELIB_TYP.lib''' file. This contains all combinational AMS elements, however they have hot yet been verified.
 This version does not include any FlipFlops.

@@ Line 56: / Line 56: @@
 ==Libraries for importing to TT==
-<big>Not final</big>
+<big>'''Not final'''</big>
 The following TT '''import''' library has been only tested with '''LBDR''' EDIF. It may or may not work with other EDIFs that are generated with this tutorial.
 This library also contains D-FlipFlop (DFCX1), which was added because of LBDR.
 [http://ati.ttu.ee/~hartz/tt_corelib_clock_modified/ tt_corelib_clock_modified]
-<big>Generated TT import library</big>
+<big>'''Generated TT import library'''</big>
 This library has been generated by a parser script from the '''CORELIB_TYP.lib''' file. This contains all combinational AMS elements, however they have hot yet been verified.
 This version does not include any FlipFlops.
 [http://ati.ttu.ee/~hartz/tt_corelib_generated/ tt_corelib_generated]

← Older revision		Revision as of 14:55, 8 June 2016
Line 53:		Line 53:
	If it is, then you should re-visit importing your design.		If it is, then you should re-visit importing your design.
	This line generates ''''INOUT'''' ports in the EDIF and TT cannot understand them.		This line generates ''''INOUT'''' ports in the EDIF and TT cannot understand them.
		+
		+
		+	==Libraries for importing to TT==
		+	<big>Not final</big>
		+	The following TT '''import''' library has been only tested with '''LBDR''' EDIF. It may or may not work with other EDIFs that are generated with this tutorial.
		+	This library also contains D-FlipFlop (DFCX1), which was added because of LBDR.
		+	[http://ati.ttu.ee/~hartz/tt_corelib_clock_modified/ tt_corelib_clock_modified]
		+
		+	<big>Generated TT import library</big>
		+	This library has been generated by a parser script from the '''CORELIB_TYP.lib''' file. This contains all combinational AMS elements, however they have hot yet been verified.
		+	This version does not include any FlipFlops.
		+	[http://ati.ttu.ee/~hartz/tt_corelib_generated/ tt_corelib_generated]

@@ Line 2: / Line 2: @@
 <br />
 <big>NB!</big>
-To first import your design into Virtuoso, use [[CDS_TT|this]] tutorial.
+<sup><big>NB!</big></sup>
 __TOC__
@@ Line 16: / Line 17: @@
 ==Bringing up Virtuoso==
-:* If you have never invoked following command in your current design folder, then there is a great possibility that you have not imported your design yet and you should follow this tutorial first.
+:* If you have never invoked following command in your current design folder, then there is a great possibility that you have not imported your design yet and you should follow [[CDS_V|this]] tutorial first.
 :: <pre>ams_cds -64 -tech c18a6 -add CORELIB -add IOLIB_6AM -add GATES_ANA</pre>
 :* If you are sure that you have invoked previously that command and you have design imported, you can bring up Virtuoso with following command.

CDS TT - Revision history

Hardi.selg: /* Libraries for importing to TT */

Hardi.selg: /* Libraries for importing to TT */

Hardi.selg: /* Libraries for importing to TT */

Hardi.selg at 14:55, 8 June 2016

Hardi.selg at 14:24, 8 June 2016

Hardi.selg at 14:21, 8 June 2016

Hardi.selg: Created page with "Purpose of this tutorial is how to export edif out of Cadence Virtuoso NB! To first import your design into Virtuoso, use this tutorial. __TOC_..."

Hardi.selg: Created page with "Purpose of this tutorial is how to export edif out of Cadence Virtuoso
NB! To first import your design into Virtuoso, use this tutorial. __TOC_..."