CPUProject - Revision history

Karljans at 13:32, 24 November 2015

2015-11-24T13:32:56Z

Karljans at 17:38, 23 November 2015

2015-11-23T17:38:01Z

Karljans: Updated front page of the CPU project to link to different implementations

2015-11-23T17:35:54Z

Updated front page of the CPU project to link to different implementations

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Siavoosh: /* Different Implementations */

2015-02-28T12:08:05Z

‎Different Implementations

Siavoosh: /* Hardware Design */

2015-02-28T11:59:54Z

‎Hardware Design

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Siavoosh: /* CPU Design */

2015-01-22T17:23:31Z

‎CPU Design

Siavoosh: /* Register File */

2015-01-09T14:57:08Z

‎Register File

Siavoosh: /* Register File */

2015-01-09T14:46:19Z

‎Register File

Siavoosh: /* Instruction Set (IS) */

2015-01-09T13:29:36Z

‎Instruction Set (IS)

Siavoosh: /* Instruction Set (IS) */

2015-01-09T12:59:55Z

‎Instruction Set (IS)

← Older revision		Revision as of 13:32, 24 November 2015
Line 5:		Line 5:
	* [[picoCPU]]: a very simple, simulation oriented CPU written in VHDL.		* [[picoCPU]]: a very simple, simulation oriented CPU written in VHDL.
	* A [[More Advanced CPU]]: a synthesizable CPU written in VHDL. It has also some more advanced features compared to the picoCPU, like stack, pipeline, etc.		* A [[More Advanced CPU]]: a synthesizable CPU written in VHDL. It has also some more advanced features compared to the picoCPU, like stack, pipeline, etc.
		+
		+	= picoAssembler =
		+	PicoAssembler is a simple, reconfigurable assembler that can be used together with the processors described above
		+	More info on this can be found on the [[PicoAssembler user manual and syntax reference]] page.

@@ Line 1: / Line 1: @@
 CPU project is one of the projects designed in department of computer engineering at TTU as a lab project to provide students with some tools for studying CPU architecture.
 Currently, there are two different CPU implementations:
 * [[picoCPU]]: a very simple, simulation oriented CPU written in VHDL.

@@ Line 170: / Line 170: @@
 *[[Non-Pipelined Version]]
 *[[Pipelined Version]]
 ==Graphics Card Design==

@@ Line 169: / Line 169: @@
 === DataPath unit===
-[[File:DPU.png|350px|thumb|right|alt= text| Fig 4: DPU block diagram]]
+[[File:DPU.jpg|350px|thumb|right|alt= text| Fig 4: DPU block diagram]]
 Datapath unit includes an Arithmetic Logical Unit (ALU), one Accumulator(ACC) and one general purpose register(Register B) and 2 multiplexers along with the flags (see Fig. 3).
 The DPU command is formed as following:

@@ Line 217: / Line 217: @@
 | 4 ||  11   || MemDATA
 |-
 |}

@@ Line 201: / Line 201: @@
 The control signals for output registers are binary encoded and are the first three bits of the operand (in case of any operation
 involving a register).
 {| class="wikitable floatright"
@@ Line 216: / Line 218: @@
 |-
 |}
 ====ALU====
 The ALU covers the following operations:

@@ Line 118: / Line 118: @@
 | 33|| Store_A_Mem || Mem[Operand] <-- A  || 10 0000  ||---- ||---- || 00 000 0010 XX || ---- || ---- || PC_out+1
 |-
-| 34|| Load_R0_Dir || R0 <-- Operand      || 10 0001  || 00000000 ||---- || 01 000 0010 XX || Operand || ---- || PC_out+1
+| 34|| Load_R0_Dir || R0 <-- Operand      || 10 0001  || 00000001 ||---- || 01 000 0010 XX || Operand || ---- || PC_out+1
 |-
-| 35||Load_R0_Mem  || R0 <-- Mem[Operand]            || 10 0010  || 00000000 ||---- || 11 000 0010 XX || ---- || Operand || PC_out+1
+| 35||Load_R0_Mem  || R0 <-- Mem[Operand]            || 10 0010  || 00000001 ||---- || 11 000 0010 XX || ---- || Operand || PC_out+1
 |-
 | 36||Load_A_R     || A <-- R(operand)               || 10 0011 ||---- || operand(2 downto 0) || 00 000 0011 XX || ---- || ---- || PC_out+1

@@ Line 118: / Line 118: @@
 | 33|| Store_A_Mem || Mem[Operand] <-- A  || 10 0000  ||---- ||---- || 00 000 0010 XX || ---- || ---- || PC_out+1
 |-
-| 34|| Load_R0_Dir || R0 <-- Operand      || 10 0001  || 00000001 ||---- || 01 000 0010 XX || Operand || ---- || PC_out+1
+| 34|| Load_R0_Dir || R0 <-- Operand      || 10 0001  || 00000000 ||---- || 01 000 0010 XX || Operand || ---- || PC_out+1
 |-
-| 35||Load_R0_Mem  || R0 <-- Mem[Operand] || 10 0010  || 00000001 ||---- || 11 000 0010 XX || ---- || Operand || PC_out+1
+| 35||Load_R0_Mem  || R0 <-- Mem[Operand]            || 10 0010  || 00000000 ||---- || 11 000 0010 XX || ---- || Operand || PC_out+1
 |-
-| 36||Load_A_R     || A <-- R(operand)    || 10 0011 ||---- || operand(2 downto 0) || 00 000 0011 XX || ---- || ---- || PC_out+1
+| 36||Load_A_R     || A <-- R(operand)               || 10 0011 ||---- || operand(2 downto 0) || 00 000 0011 XX || ---- || ---- || PC_out+1
 |-
-| 37||Load_R_A     || R(operand) <-- A    || 10 0100 || operand(7 downto 0) ||---- || 10 000 0010 XX || ---- || ---- || PC_out+1
+| 37||Load_R_A     || R(operand) <-- A               || 10 0100 || operand(7 downto 0) ||---- || 10 000 0010 XX || ---- || ---- || PC_out+1
 |-
-| 38||Load_Ind_A   || A <-- M[A]          || 10 0101 ||---- ||---- || 00 000 0011 00 || ---- || A || PC_out+1
+| 38||Load_Ind_A   || A <-- M[A]                     || 10 0101 ||---- ||---- || 00 000 0011 00 || ---- || A || PC_out+1
 |-
-| 39|| PUSH || Mem [0 + SP] <--- A,SP <--- SP + 1 || 11 1100 ||---- ||---- || 00	000 0010 XX || ---- || ---- || PC_out+1
+| 39|| PUSH || Mem [0 + SP] <--- A,SP <--- SP + 1    || 11 1100 ||---- ||---- || 00	000 0010 XX || ---- || ---- || PC_out+1
 |-
 | 40|| POP || A <--- Mem [0 + SP - 1],SP <--- SP - 1 || 11 1101 ||---- ||---- || 00 000 0011 00 || ---- || SP - 1 || PC_out+1
 |-
-| 41|| NOP || NOP || 11 1110 ||---- ||---- || 00	000 0010 XX || ---- || ---- || PC_out+1
+| 41|| NOP || NOP                                    || 11 1110 ||---- ||---- || 00 000 0010 XX || ---- || ---- || PC_out+1
 |-
-| 42|| HALT || HALT || 11 1111 ||---- ||---- || 00	000 0010 XX || ---- || ---- || PC
+| 42|| HALT || HALT                                  || 11 1111 ||---- ||---- || 00 000 0010 XX || ---- || ---- || PC
 |}
 ==== Implementation of complex instructions====