Glossary - Revision history

193.40.194.222 at 19:52, 20 April 2010

2010-04-20T19:52:52Z

193.40.194.222 at 19:14, 20 April 2010

2010-04-20T19:14:27Z

193.40.194.222 at 19:10, 20 April 2010

2010-04-20T19:10:19Z

193.40.194.222 at 19:07, 20 April 2010

2010-04-20T19:07:45Z

193.40.194.222 at 19:06, 20 April 2010

2010-04-20T19:06:56Z

193.40.194.222 at 19:05, 20 April 2010

2010-04-20T19:05:13Z

193.40.194.222 at 19:01, 20 April 2010

2010-04-20T19:01:29Z

193.40.194.222 at 18:59, 20 April 2010

2010-04-20T18:59:46Z

193.40.194.222 at 18:52, 20 April 2010

2010-04-20T18:52:27Z

193.40.194.222 at 10:59, 10 February 2010

2010-02-10T10:59:59Z

@@ Line 33: / Line 33: @@
 |-
 | HW 	|| Hardware
 |-
 | IEEE 	|| Institute of Electrical and Electronic Engineers, Inc.

@@ Line 38: / Line 38: @@
 | IP (core) 	|| Intellectual Property (core), synonymous with Virtual Component (VC)
 |-
-| IPC || Inter Process Communication
+| IPC   || Inter Process Communication
 |-
 | ISA (model) 	|| Instruction Set Architecture (model)
@@ Line 65: / Line 65: @@
 |-
 | Synopsys VSS || Synopsys VHDL System Simulator
 |-
 | UML 	|| Universal Modeling Language
 |-
-| VCI || VHDL-C Interface
+| VCI   || VHDL-C Interface
 |-
 | VHDL 	|| Very high speed Hardware Description Language

@@ Line 4: / Line 4: @@
 | ASIC 	|| Application Specific Integrated Circuit
 |-
 | ASM 	|| Abstract State Machines
 |-
 | CDFG 	|| Control Data Flow Graph

@@ Line 36: / Line 36: @@
 | IP (core) 	|| Intellectual Property (core), synonymous with Virtual Component (VC)
 |-
-| IPC || Inter Process communication
+| IPC || Inter Process Communication
 |-
 | ISA (model) 	|| Instruction Set Architecture (model)
@@ Line 65: / Line 65: @@
 |-
 | UML 	|| Universal Modeling Language
 |-
 | VHDL 	|| Very high speed Hardware Description Language

@@ Line 35: / Line 35: @@
 |-
 | IP (core) 	|| Intellectual Property (core), synonymous with Virtual Component (VC)
 |-
 | ISA (model) 	|| Instruction Set Architecture (model)

@@ Line 57: / Line 57: @@
 |-
 | SW 	|| Software
 |-
 | Synopsys VSS || Synopsys VHDL System Simulator

@@ Line 6: / Line 6: @@
 | ASM 	|| Abstract State Machines
 |-
-| EDA 	|| Electronic Design Automation
+| CDFG 	|| Control Data Flow Graph
 |-
 | CLB 	|| Configurable Logic Block (of FPGA)
@@ Line 16: / Line 16: @@
 | DSP 	|| Digital Signal Processor
 |-
-| Firm core || (or semi-hard core) IP-s carrying placement data but configurable for various applications
+| EDA 	|| Electronic Design Automation
 |-
 | ESL 	|| Electronic System Level
 |-
 | FPGA 	|| Field Programmable Gate Array
@@ Line 27: / Line 29: @@
 |-
 | HSCO 	|| Hardware-Software Co-Design
 |-
 | IEEE 	|| Institute of Electrical and Electronic Engineers, Inc.
@@ Line 47: / Line 51: @@
 |-
 | SLB 	|| System Level Block
 |-
 | SoC 	|| System-on-Chip
 |-
 | SW 	|| Software
 |-
 | Synopsys VSS || Synopsys VHDL System Simulator
 |-
 | UML 	|| Universal Modeling Language
@@ Line 69: / Line 71: @@
 |-
 | VSIA 	|| Virtual Socket Initiative Alliance
 |-
 | XPP 	|| eXtreme Processing Platform of PACT
 |}

@@ Line 1: / Line 1: @@
 {|
-| Hard core ||	Physical manifestations of the IP design
+| ACM 	|| Adaptive Computing Machine
 |-
 | CSP 	|| Communicating Sequential Processes
 |-
 | Firm core || (or semi-hard core) IP-s carrying placement data but configurable for various applications
@@ Line 8: / Line 20: @@
 | ESL 	|| Electronic System Level
 |-
-| CLB 	|| Configurable Logic Block (of FPGA)
+| FPGA 	|| Field Programmable Gate Array
 |-
 | HLS 	|| High Level Synthesis
 |-
 | IEEE 	|| Institute of Electrical and Electronic Engineers, Inc.
 |-
 | IP (core) 	|| Intellectual Property (core), synonymous with Virtual Component (VC)
 |-
 | ISA (model) 	|| Instruction Set Architecture (model)
 |-
-| ASIC 	|| Application Specific Integrated Circuit
+| LRM 	|| Language Reference Manual
 |-
-| ACM 	|| Adaptive Computing Machine
+| netlist 	|| A list of logic gates and associated interconnections making up an integrated circuit
 |-
-| LRM 	|| Language Reference Manual
+| NoC 	|| Network-on-Chip
 |-
 | PCB 	|| Printed Circuit Board
 |-
-| netlist 	|| A list of logic gates and associated interconnections making up an integrated circuit
+| RTL 	|| Register-Transfer Level
 |-
-| SoC 	|| System-on-Chip
+| SDL 	|| Specification and Description Language, standardized by ITU (International Telecommunication Union)
 |-
-| SW 	|| Software
+| SLB 	|| System Level Block
 |-
 | Soft core 	|| IP presented as a netlist or HDL code
 |-
-| DSM 	|| Deep SubMicron
+| SoC 	|| System-on-Chip
 |-
-| DSP 	|| Digital Signal Processor
+| SW 	|| Software
 |-
 | HW 	|| Hardware
@@ Line 50: / Line 60: @@
 | UML 	|| Universal Modeling Language
 |-
-| VSIA 	|| Virtual Socket Initiative Alliance
+| VHDL 	|| Very high speed Hardware Description Language
 |-
-| RTL 	|| Register-Transfer Level
+| VITAL || VHDL Initiative Toward ASIC Libraries
 |-
-| CDFG 	|| Control Data Flow Graph
+| VLIW 	|| Very Long Instruction Word (processor)
 |-
-| NoC 	|| Network-on-Chip
+| VLSI 	|| Very Large Scale Integration (Integrated Circuit)
 |-
-| SDL 	|| Specification and Description Language, standardized by ITU (International Telecommunication Union)
+| VSIA 	|| Virtual Socket Initiative Alliance
 |-
-| HSCO 	|| Hardware-Software Co-Design
+| CDFG 	|| Control Data Flow Graph
-|-
-| SLB 	|| System Level Block
-|-
-| ASM 	|| Abstract State Machines
-|-
-| EDA 	|| Electronic Design Automation
 |-
 | XPP 	|| eXtreme Processing Platform of PACT
 |}

← Older revision		Revision as of 10:59, 10 February 2010
Line 1:		Line 1:
−	* HSCO - Hardware-Software Co-Design	+	{\|
		+	\| Hard core \|\| Physical manifestations of the IP design
		+	\|-
		+	\| CSP \|\| Communicating Sequential Processes
		+	\|-
		+	\| Firm core \|\| (or semi-hard core) IP-s carrying placement data but configurable for various applications
		+	\|-
		+	\| ESL \|\| Electronic System Level
		+	\|-
		+	\| CLB \|\| Configurable Logic Block (of FPGA)
		+	\|-
		+	\| HLS \|\| High Level Synthesis
		+	\|-
		+	\| IEEE \|\| Institute of Electrical and Electronic Engineers, Inc.
		+	\|-
		+	\| IP (core) \|\| Intellectual Property (core), synonymous with Virtual Component (VC)
		+	\|-
		+	\| VHDL \|\| Very high speed Hardware Description Language
		+	\|-
		+	\| VLIW \|\| Very Long Instruction Word (processor)
		+	\|-
		+	\| VLSI \|\| Very Large Scale Integration (Integrated Circuit)
		+	\|-
		+	\| ISA (model) \|\| Instruction Set Architecture (model)
		+	\|-
		+	\| ASIC \|\| Application Specific Integrated Circuit
		+	\|-
		+	\| ACM \|\| Adaptive Computing Machine
		+	\|-
		+	\| LRM \|\| Language Reference Manual
		+	\|-
		+	\| PCB \|\| Printed Circuit Board
		+	\|-
		+	\| netlist \|\| A list of logic gates and associated interconnections making up an integrated circuit
		+	\|-
		+	\| SoC \|\| System-on-Chip
		+	\|-
		+	\| SW \|\| Software
		+	\|-
		+	\| Soft core \|\| IP presented as a netlist or HDL code
		+	\|-
		+	\| DSM \|\| Deep SubMicron
		+	\|-
		+	\| DSP \|\| Digital Signal Processor
		+	\|-
		+	\| HW \|\| Hardware
		+	\|-
		+	\| UML \|\| Universal Modeling Language
		+	\|-
		+	\| VSIA \|\| Virtual Socket Initiative Alliance
		+	\|-
		+	\| RTL \|\| Register-Transfer Level
		+	\|-
		+	\| CDFG \|\| Control Data Flow Graph
		+	\|-
		+	\| NoC \|\| Network-on-Chip
		+	\|-
		+	\| SDL \|\| Specification and Description Language, standardized by ITU (International Telecommunication Union)
		+	\|-
		+	\| HSCO \|\| Hardware-Software Co-Design
		+	\|-
		+	\| SLB \|\| System Level Block
		+	\|-
		+	\| ASM \|\| Abstract State Machines
		+	\|-
		+	\| EDA \|\| Electronic Design Automation
		+	\|-
		+	\| XPP \|\| eXtreme Processing Platform of PACT
		+	\|-
		+	\| FPGA \|\| Field Programmable Gate Array
		+	\|}