Difference between revisions of "Glossary"
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| + | | ACM || Adaptive Computing Machine | ||
| + | |- | ||
| + | | ASIC || Application Specific Integrated Circuit | ||
| + | |- | ||
| + | | ASM || Abstract State Machines | ||
| + | |- | ||
| + | | BFM || Bus Functional Model | ||
| + | |- | ||
| + | | CDFG || Control Data Flow Graph | ||
| + | |- | ||
| + | | CLB || Configurable Logic Block (of FPGA) | ||
| + | |- | ||
| + | | CSP || Communicating Sequential Processes | ||
| + | |- | ||
| + | | DSM || Deep SubMicron | ||
| + | |- | ||
| + | | DSP || Digital Signal Processor | ||
| + | |- | ||
| + | | EDA || Electronic Design Automation | ||
| + | |- | ||
| + | | ESL || Electronic System Level | ||
| + | |- | ||
| + | | Firm core || (or semi-hard core) IP-s carrying placement data but configurable for various applications | ||
| + | |- | ||
| + | | FPGA || Field Programmable Gate Array | ||
| + | |- | ||
| + | | Hard core || Physical manifestations of the IP design | ||
| + | |- | ||
| + | | HLS || High Level Synthesis | ||
| + | |- | ||
| + | | HSCO || Hardware-Software Co-Design | ||
| + | |- | ||
| + | | HW || Hardware | ||
| + | |- | ||
| + | | ICE || In Circuit Emulator | ||
| + | |- | ||
| + | | IEEE || Institute of Electrical and Electronic Engineers, Inc. | ||
| + | |- | ||
| + | | IP (core) || Intellectual Property (core), synonymous with Virtual Component (VC) | ||
| + | |- | ||
| + | | IPC || Inter Process Communication | ||
| + | |- | ||
| + | | ISA (model) || Instruction Set Architecture (model) | ||
| + | |- | ||
| + | | LRM || Language Reference Manual | ||
| + | |- | ||
| + | | netlist || A list of logic gates and associated interconnections making up an integrated circuit | ||
| + | |- | ||
| + | | NoC || Network-on-Chip | ||
| + | |- | ||
| + | | PCB || Printed Circuit Board | ||
| + | |- | ||
| + | | RTL || Register-Transfer Level | ||
| + | |- | ||
| + | | SDL || Specification and Description Language, standardized by ITU (International Telecommunication Union) | ||
| + | |- | ||
| + | | SLB || System Level Block | ||
| + | |- | ||
| + | | SoC || System-on-Chip | ||
| + | |- | ||
| + | | Soft core || IP presented as a netlist or HDL code | ||
| + | |- | ||
| + | | SW || Software | ||
| + | |- | ||
| + | | Synopsys VCS || Synopsys Verilog Simulator | ||
| + | |- | ||
| + | | Synopsys VSS || Synopsys VHDL System Simulator | ||
| + | |- | ||
| + | | UCF || User Constraint File | ||
| + | |- | ||
| + | | UML || Universal Modeling Language | ||
| + | |- | ||
| + | | VCI || VHDL-C Interface | ||
| + | |- | ||
| + | | VHDL || Very high speed Hardware Description Language | ||
| + | |- | ||
| + | | VITAL || VHDL Initiative Toward ASIC Libraries | ||
| + | |- | ||
| + | | VLIW || Very Long Instruction Word (processor) | ||
| + | |- | ||
| + | | VLSI || Very Large Scale Integration (Integrated Circuit) | ||
| + | |- | ||
| + | | VSIA || Virtual Socket Initiative Alliance | ||
| + | |- | ||
| + | | XPP || eXtreme Processing Platform of PACT | ||
| + | |} | ||
Latest revision as of 21:52, 20 April 2010
| ACM | Adaptive Computing Machine |
| ASIC | Application Specific Integrated Circuit |
| ASM | Abstract State Machines |
| BFM | Bus Functional Model |
| CDFG | Control Data Flow Graph |
| CLB | Configurable Logic Block (of FPGA) |
| CSP | Communicating Sequential Processes |
| DSM | Deep SubMicron |
| DSP | Digital Signal Processor |
| EDA | Electronic Design Automation |
| ESL | Electronic System Level |
| Firm core | (or semi-hard core) IP-s carrying placement data but configurable for various applications |
| FPGA | Field Programmable Gate Array |
| Hard core | Physical manifestations of the IP design |
| HLS | High Level Synthesis |
| HSCO | Hardware-Software Co-Design |
| HW | Hardware |
| ICE | In Circuit Emulator |
| IEEE | Institute of Electrical and Electronic Engineers, Inc. |
| IP (core) | Intellectual Property (core), synonymous with Virtual Component (VC) |
| IPC | Inter Process Communication |
| ISA (model) | Instruction Set Architecture (model) |
| LRM | Language Reference Manual |
| netlist | A list of logic gates and associated interconnections making up an integrated circuit |
| NoC | Network-on-Chip |
| PCB | Printed Circuit Board |
| RTL | Register-Transfer Level |
| SDL | Specification and Description Language, standardized by ITU (International Telecommunication Union) |
| SLB | System Level Block |
| SoC | System-on-Chip |
| Soft core | IP presented as a netlist or HDL code |
| SW | Software |
| Synopsys VCS | Synopsys Verilog Simulator |
| Synopsys VSS | Synopsys VHDL System Simulator |
| UCF | User Constraint File |
| UML | Universal Modeling Language |
| VCI | VHDL-C Interface |
| VHDL | Very high speed Hardware Description Language |
| VITAL | VHDL Initiative Toward ASIC Libraries |
| VLIW | Very Long Instruction Word (processor) |
| VLSI | Very Large Scale Integration (Integrated Circuit) |
| VSIA | Virtual Socket Initiative Alliance |
| XPP | eXtreme Processing Platform of PACT |
