Difference between revisions of "Pipelined Version"
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[[File:PipelinedPicoCPU.jpg|400px|thumb|right|alt= text| Fig 1: System Block Diagram]] | [[File:PipelinedPicoCPU.jpg|400px|thumb|right|alt= text| Fig 1: System Block Diagram]] | ||
| + | [[File:DifferentPipesState.jpg|500px|thumb|right|alt= text| Fig 2: Different Pipes States]] | ||
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| + | The Building Components are the same as the non-pipeline version. The only major difference is the control unit | ||
| + | which has the pipes. | ||
===Current versions (VHDL)=== | ===Current versions (VHDL)=== | ||
Latest revision as of 18:50, 28 February 2015
The Building Components are the same as the non-pipeline version. The only major difference is the control unit which has the pipes.
Current versions (VHDL)
- 28 Feb 2015: 8-bit pipelined
Future plans
- Pipelining PC and SP
- Adding Branch prediction etc.
- Still needs NOPs inserted after JMPs and HALT (To prevent data hazards.)
