Difference between revisions of "CPUProject"

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m (→‎DataPath unit)
(→‎Instruction Set (IS))
Line 32: Line 32:
 
! Instruction !! Register Transfer Language !! OpCode !! DPU Command !! Data To DPU !! MemAddress !!  Next PC
 
! Instruction !! Register Transfer Language !! OpCode !! DPU Command !! Data To DPU !! MemAddress !!  Next PC
 
|-
 
|-
−
| Add_A_B || A <-- A + B                    || Example || 00 000 0000 10 || ----    || ---- || PC_out+1   
+
| Add_A_B || A <-- A + B                    || XX00 0000 || 00 000 0000 10 || ----    || ----   || PC_out+1   
 
|-
 
|-
−
| Add_A_Mem || A <-- A + Mem[Operand]      || Example || 00 000 0000 00 || ----    || Operand || PC_out+1   
+
| Add_A_Mem || A <-- A + Mem[Operand]      || XX00 0001 || 00 000 0000 00 || ----    || Operand || PC_out+1   
 
|-
 
|-
−
| Add_A_Dir || A <-- A + Operand            || Example || 00 000 0000 01 || Operand || ---- || PC_out+1   
+
| Add_A_Dir || A <-- A + Operand            || XX00 0010 || 00 000 0000 01 || Operand || ----   || PC_out+1   
 
|-
 
|-
−
| Sub_A_B || A <-- A - B                    || Example || 00 000 0001 10 || ----    || ---- || Example   
+
| Sub_A_B || A <-- A - B                    || XX00 0011 || 00 000 0001 10 || ----    || ----   || Example   
 
|-
 
|-
 
| Sub_A_Mem || A <-- A - Mem[Operand]      || Example || 00 000 0001 00 || ----    || Operand || PC_out+1   
 
| Sub_A_Mem || A <-- A - Mem[Operand]      || Example || 00 000 0001 00 || ----    || Operand || PC_out+1   
Line 48: Line 48:
 
| DecA || A <-- A - 1                      || Example || 00 000 0001 11 || ----    || ---- || PC_out+1  
 
| DecA || A <-- A - 1                      || Example || 00 000 0001 11 || ----    || ---- || PC_out+1  
 
|-
 
|-
−
| And_A_B || A <-- A and B                  || Example || 00 000 0100 10 || ----   || ---- || PC_out+1
+
| ShiftArithR || A <-- A(7) & A(7 downto 1)  || Example || 00 000 0111 00 || ---- || ---- || PC_out+1  
 
|-
 
|-
−
| OR_A_B || A <-- A or B                    || Example || 00 000 0101 10 || ----   || ---- || PC_out+1
+
| ShiftArithL || A <-- A(7) & A(5 downto 0)& '0' || Example || 00 000 1000 00 || ---- || ---- || PC_out+1  
 
|-
 
|-
−
| XOR_A_B || A <-- A xor B                  || Example || 00 000 0110 10 || ----   || ---- || PC_out+1
+
| ShiftA_R || A <-- A(6 downto 0)& '0' || Example || 00 000 1010 00 || ---- || ---- || PC_out+1  
 
|-
 
|-
−
| FlipA || A <-- not (A)                   || Example || 00 000 1100 00 || ----   || ---- || PC_out+1
+
| ShiftA_L || A <-- '0' & A(7 downto 1) || Example || 00 000 1011 00 || ---- || ---- || PC_out+1  
 
|-
 
|-
−
| NegA || A <-- not(A) + 1                  || Example || Example || ---- || ---- || PC_out+1
+
| RRC || A <-- C & A(7 downto 1) ,C<--  A(0) || Example || 00 000 1110 XX || ---- || ---- || PC_out+1    
 
|-
 
|-
−
| Jmp || PC <-- Operand                    || Example || Example || ---- || ---- || Depends 
+
| RLC || A <-- A(6 downto 0) & C ,C<--  A(7) || Example || 00 000 1111 XX || ---- || ---- || PC_out+1 
 
|-
 
|-
−
| JmpZ || if Z = 1: PC <-- Operand || Example || Example || ---- || ---- || Depends  
+
| And_A_B || A <-- A and B                  || Example || 00 000 0100 10 || ----   || ---- || PC_out+1  
 
|-
 
|-
−
| JmpOV || if OV = 1: PC <-- Operand || Example || Example || ---- || ---- || Depends  
+
| OR_A_B || A <-- A or B                    || Example || 00 000 0101 10 || ----   || ---- || PC_out+1  
 
|-
 
|-
−
| Jmp_rel || PC <-- PC + Operand  || Example || Example || ---- || ---- || Depends  
+
| XOR_A_B || A <-- A xor B                  || Example || 00 000 0110 10 || ----   || ---- || PC_out+1  
 
|-
 
|-
−
| JMPEQ || if EQ = 1: PC <-- Operand || Example || Example || ---- || ---- || Depends  
+
| FlipA || A <-- not (A)                    || Example || 00 000 1100 00 || ----   || ---- || PC_out+1  
 
|-
 
|-
−
| ClearZ || Z <--- 0 || Example || Example || ---- || ---- ||   PC_out+1   
+
| NegA || A <-- not(A) + 1                  || Example || 00 000 1001 00 || ---- || ---- || PC_out+1   
 
|-
 
|-
−
| ClearOV || OV <--- 0 || Example || Example || ---- || ---- || PC_out+1   
+
| Jmp || PC <-- Operand                    || Example || 00 000 0010 XX || ---- || ---- || Depends 
 
|-
 
|-
−
| LoadPC  || PC <---- A || Example || Example || ---- || ---- || A  
+
| JmpZ || if Z = 1: PC <-- Operand || Example || 00 000 0010 XX || ---- || ---- || Depends  
 
|-
 
|-
−
| SavePC || A <---- PC || Example || Example || PC || ---- || PC_out+1   
+
| JmpOV || if OV = 1: PC <-- Operand || Example || 00 000 0010 XX || ---- || ---- || Depends 
 
|-
 
|-
−
| ShiftArithR || A <-- A(7) & A(7 downto 1)  || Example || Example || ---- || ---- || PC_out+1   
+
| JmpC || if C = 1: PC <-- Operand || Example || 00 000 0010 XX || ---- || ---- || Depends 
 
|-
 
|-
−
| ShiftArithL || A <-- A(7) & A(5 downto 0)& '0' || Example || Example || ---- || ---- || PC_out+1   
+
| Jmp_rel || PC <-- PC + Operand  || Example || 00 000 0010 XX || ---- || ---- || Depends 
 
|-
 
|-
−
| ShiftA_R || A <-- A(6 downto 0)& '0' || Example || Example || ---- || ---- || PC_out+1   
+
| JMPEQ || if EQ = 1: PC <-- Operand || Example || 00 000 0010 XX || ---- || ---- || Depends 
 
|-
 
|-
−
| ShiftA_L || A <-- '0' & A(7 downto 1)  || Example || Example || ---- || ---- || PC_out+1  
+
| ClearZ || Z <--- 0 || Example || 00 000 0010 XX || ---- || ---- ||   PC_out+1
 
|-
 
|-
−
| Load_A_Mem || A <-- Mem[Operand] || Example || Example || ---- || Operand || PC_out+1     
+
| ClearOV || OV <--- 0 || Example || 00 000 0010 XX || ---- || ---- || PC_out+1     
 
|-
 
|-
−
| Store_A_Mem || Mem[Operand] <-- A || Example || 00 000 0010 -- || ---- || Operand || PC_out+1     
+
| ClearC || C <--- 0 || Example || 00 100 0010 XX || ---- || ---- || PC_out+1     
 
|-
 
|-
−
| Load_B_Dir || B <-- Operand || Example || 00 000 0010 -- || Operand || ---- || PC_out+1  
+
| ClearACC || ACC <-- 0 || Example || 00 000 1101 XX || ---- || ---- || PC_out+1  
 
|-
 
|-
−
| Load_B_Mem || B <-- Mem[Operand] || Example || 00 000 0010 -- || ---- || Operand || PC_out+1   
+
| LoadPC  || PC <---- A || Example || 00 000 0010 XX || ---- || ---- || A 
 
|-
 
|-
−
| JmpC || if C = 1: PC <-- Operand || Example || 00 000 0010 -- || ---- || ---- || Depends 
+
| SavePC || A <---- PC || Example || 00 000 0011 01 || PC || ---- || PC_out+1   
 
|-
 
|-
−
| ClearC || C <--- 0 || Example || 00 000 0010 -- || ---- || ---- || PC_out+1     
+
| Load_A_Mem || A <-- Mem[Operand] || Example || 00 000 0011 00 || ---- || Operand || PC_out+1     
 
|-
 
|-
−
| ClearACC || ACC <-- 0 || Example || Example || ---- || ---- || PC_out+1     
+
| Store_A_Mem || Mem[Operand] <-- A || Example || 00 000 0010 XX || ---- || Operand || PC_out+1     
 
|-
 
|-
−
| RRC || A <-- C & A(7 downto 1) ,C<--  A(0)  || Example || Example || ---- || ---- || PC_out+1    
+
| Load_B_Dir || B <-- Operand || Example || 01 000 0010 XX || Operand || ---- || PC_out+1  
 
|-
 
|-
−
| RLC || A <-- A(6 downto 0) & C ,C<--  A(7) || Example || Example || ---- || ---- || PC_out+1  
+
| Load_B_Mem || B <-- Mem[Operand] || Example || 11 000 0010 XX || ---- || Operand || PC_out+1    
 
|-
 
|-
−
| PUSH || Mem [0 + SP] <--- A,SP <--- SP + 1 || Example || 00 000 0010 -- || ---- || SP || PC_out+1   
+
| PUSH || Mem [0 + SP] <--- A,SP <--- SP + 1 || Example || 00 000 0010 XX || ---- || SP || PC_out+1   
 
|-
 
|-
−
| POP || A <--- Mem [0 + SP - 1],SP <--- SP - 1 || Example || Example || ---- || SP - 1 || PC_out+1   
+
| POP || A <--- Mem [0 + SP - 1],SP <--- SP - 1 || Example || 00 000 0011 00 || ---- || SP - 1 || PC_out+1   
 
|-
 
|-
−
| NOP || NOP || Example || 00 000 0010 -- || ---- || ---- || PC_out+1   
+
| NOP || NOP || Example || 00 000 0010 XX || ---- || ---- || PC_out+1   
 
|-
 
|-
−
| HALT || HALT || Example || 00 000 0010 -- || ---- || ---- || PC   
+
| HALT || HALT || Example || 00 000 0010 XX || ---- || ---- || PC   
 
|}
 
|}
 
===Other instructions implementation===
 
===Other instructions implementation===

Revision as of 09:39, 5 December 2014

CPU project is one of the projects designed in department of computer engineering at TTU as a lab project. The main aims of this project are:

  • Developing a generic CPU without any fancy feature
  • Writing a compiler for it
  • Compiling GCC for this architecture
  • Booting a light linux on it

CPU Design

Functionality Requirements

The CPU is supposed to be able to perform the following operations:

  • Addition/Subtraction
  • Increment/Decrement
  • Arithmetic and Logical Shift
  • Bitwise AND, OR, XOR and NOT
  • Negation
  • Load/Store
  • Unconditional Branch (jump)
  • Branch if zero / Branch if Overflow / Branch if Carry
  • Clear Registers/Flags
  • PUSH / POP
  • NOP/HALT

Architecture

Instruction Format

Our CPU's instuction has 8 bit of upcode and one operand that can be as long as 32 bit. First 3 bits of OPcode are at the moment reserved.

Instruction Set (IS)

The following instrcutions designed for the CPU:

Instruction Register Transfer Language OpCode DPU Command Data To DPU MemAddress Next PC
Add_A_B A <-- A + B XX00 0000 00 000 0000 10 ---- ---- PC_out+1
Add_A_Mem A <-- A + Mem[Operand] XX00 0001 00 000 0000 00 ---- Operand PC_out+1
Add_A_Dir A <-- A + Operand XX00 0010 00 000 0000 01 Operand ---- PC_out+1
Sub_A_B A <-- A - B XX00 0011 00 000 0001 10 ---- ---- Example
Sub_A_Mem A <-- A - Mem[Operand] Example 00 000 0001 00 ---- Operand PC_out+1
Sub_A_Dir A <-- A - Operand Example 00 000 0001 01 Operand ---- PC_out+1
IncA A <-- A + 1 Example 00 000 0000 11 ---- ---- PC_out+1
DecA A <-- A - 1 Example 00 000 0001 11 ---- ---- PC_out+1
ShiftArithR A <-- A(7) & A(7 downto 1) Example 00 000 0111 00 ---- ---- PC_out+1
ShiftArithL A <-- A(7) & A(5 downto 0)& '0' Example 00 000 1000 00 ---- ---- PC_out+1
ShiftA_R A <-- A(6 downto 0)& '0' Example 00 000 1010 00 ---- ---- PC_out+1
ShiftA_L A <-- '0' & A(7 downto 1) Example 00 000 1011 00 ---- ---- PC_out+1
RRC A <-- C & A(7 downto 1) ,C<-- A(0) Example 00 000 1110 XX ---- ---- PC_out+1
RLC A <-- A(6 downto 0) & C ,C<-- A(7) Example 00 000 1111 XX ---- ---- PC_out+1
And_A_B A <-- A and B Example 00 000 0100 10 ---- ---- PC_out+1
OR_A_B A <-- A or B Example 00 000 0101 10 ---- ---- PC_out+1
XOR_A_B A <-- A xor B Example 00 000 0110 10 ---- ---- PC_out+1
FlipA A <-- not (A) Example 00 000 1100 00 ---- ---- PC_out+1
NegA A <-- not(A) + 1 Example 00 000 1001 00 ---- ---- PC_out+1
Jmp PC <-- Operand Example 00 000 0010 XX ---- ---- Depends
JmpZ if Z = 1: PC <-- Operand Example 00 000 0010 XX ---- ---- Depends
JmpOV if OV = 1: PC <-- Operand Example 00 000 0010 XX ---- ---- Depends
JmpC if C = 1: PC <-- Operand Example 00 000 0010 XX ---- ---- Depends
Jmp_rel PC <-- PC + Operand Example 00 000 0010 XX ---- ---- Depends
JMPEQ if EQ = 1: PC <-- Operand Example 00 000 0010 XX ---- ---- Depends
ClearZ Z <--- 0 Example 00 000 0010 XX ---- ---- PC_out+1
ClearOV OV <--- 0 Example 00 000 0010 XX ---- ---- PC_out+1
ClearC C <--- 0 Example 00 100 0010 XX ---- ---- PC_out+1
ClearACC ACC <-- 0 Example 00 000 1101 XX ---- ---- PC_out+1
LoadPC PC <---- A Example 00 000 0010 XX ---- ---- A
SavePC A <---- PC Example 00 000 0011 01 PC ---- PC_out+1
Load_A_Mem A <-- Mem[Operand] Example 00 000 0011 00 ---- Operand PC_out+1
Store_A_Mem Mem[Operand] <-- A Example 00 000 0010 XX ---- Operand PC_out+1
Load_B_Dir B <-- Operand Example 01 000 0010 XX Operand ---- PC_out+1
Load_B_Mem B <-- Mem[Operand] Example 11 000 0010 XX ---- Operand PC_out+1
PUSH Mem [0 + SP] <--- A,SP <--- SP + 1 Example 00 000 0010 XX ---- SP PC_out+1
POP A <--- Mem [0 + SP - 1],SP <--- SP - 1 Example 00 000 0011 00 ---- SP - 1 PC_out+1
NOP NOP Example 00 000 0010 XX ---- ---- PC_out+1
HALT HALT Example 00 000 0010 XX ---- ---- PC

Other instructions implementation

the follwoing instructions can be also implemented with the ones in IS:

  • Call "function_name": 
PUSH
SavePC
Push
Jmp "function address"
POP
  • Return:
POP
Add_A_Dir 4
LoadPC

DataPath unit

Flags

  • Zero Flag (Z)
  • Overflow Flag (OV):
  • Carry Flag (C):

Control unit

Instruction Memory (ROM)

Data Memory

Functional Testing

Assembler

Compiler

Retrieved from "https://strudel.pld.ttu.ee/wiki/e/index.php?title=CPUProject&oldid=1932"