Revision as of 17:46, 9 January 2015

CPU project is one of the projects designed in department of computer engineering at TTU as a lab project. The main aims of this project are:

• Developing a simple generic CPU
• Developing peripherals for it
• Writing a compiler and assembler for it
• Compiling GCC for this architecture
• Booting a lightweight linux on it

This project has many interesting points and which can be used for laboratories in different courses.

Hardware Design

CPU Design

Fig 1: System Block Diagram

Fig 2: System Architecture

Functionality Requirements

The CPU is supposed to be able to perform the following operations:

• Addition/Subtraction
• Increment/Decrement
• Arithmetic and Logical Shift and Rotate through carry
• Bitwise AND, OR, XOR and NOT
• Negation
• Load/Store
• Unconditional Branch (jump)
• Branch if zero / Branch if Overflow / Branch if Carry/ Branch if Equal
• Clear Registers/Flags
• PUSH / POP
• NOP/HALT

It can use these operations to build more sophisticated operations later.

Architecture

The architecture of this CPU is based on Harvard architecture which has separate instruction and data memory. The instructions are assumed to be in the instruction memory before boot.

Instruction Format

Our CPU's instruction has 8 bit of Op-code and one operand that can be as long as 32 bit. First 2 bits of OP-code are at the moment reserved.

Fig 3: Instruction format

Addressing Modes

The following Addressing modes are supported in out processor:

• direct: program counter jumps to an address directly provided to it through instruction's operand
• relative: the program counter will jump to a location relative to its current location
• indirect: program counter will jump to an address stored in a memory location
• register: program counter will jump to an address stored in a register
• indexed: program counter will jump to an address stored in the memory with address stored in a register

Instruction Set (IS)

The following instructions designed for the CPU:

Implementation of complex instructions

the following instructions can be also implemented with the ones in IS:

• Call "function_name":

PUSH
SavePC
Push
Jmp "function address"
POP  

• Return:

POP
Add_A_Dir 4
LoadPC

• IndJMP "MemAddress":

PUSH
Load_A_Mem "MemAddress"
LoadPC

Note: its important to POP back the ACC value on the jump destination.

• JmpR:

PUSH
Load_A_R "----"
LoadPC

Note: its important to POP back the ACC value on the jump destination.

• JmpIndx:

PUSH
Load_Ind_A
LoadPC

Note: its important to POP back the ACC value on the jump destination.

DataPath unit

Fig 4: DPU block diagram

Datapath unit includes an Arithmetic Logical Unit (ALU), one Accumulator(ACC) and one general purpose register(Register B) and 2 multiplexers along with the flags (see Fig. 3). The DPU command is formed as following:

ALU Multiplexer

The ALU multiplexer chooses the inputs according to the table 2.

Register File

Fig 5: Register File Schematic

The schematic of register file is show in figure 5. The Input multiplexer chooses the inputs according to the table 3. Each register has a small 2 to 1 multiplexer that chooses whether the input is coming from the outside or keeping the old value. The control for 2 to 1 multiplexers is one hot code that comes from the first 8 bits of operand (this will be used only during writing to Reg-file). The control signals for output registers are binary encoded and are the first three bits of the operand (in case of any operation involving a register). R0 is the only register that can be loaded directly by user from memory or operand since this operation needs source and destination address and our instruction format can not support it. The other registers can be only loaded via Acc.

ALU

The ALU covers the following operations:

For addition/subtraction a ripple carry model is made out of chain of full adders.

Flags

In DPU has the following flags:

• Zero Flag (Z): will be set if the result of the operation is zero
• Overflow Flag (OV): will be set if an overflow happens in signed operations (as an example if we have 8 bit addition of 82+91 the answer we expect is 173 but the result would be interpreted as -45). Overflow flag can be realized in the following way:
• Carry Flag (C): will be set if the unsigned addition or subtraction results in a carry.
• Equal Flag (EQ): will be set if ACC value is equal to the operand

To clear flags,the SetFlag commands are used in DPU command (see table 5).

Instruction Memory (ROM)

Instruction memory is a read only memory that user will fill in the beginning.

Data Memory

Fig 6: Data Memory block diagram

Data memory is made out of blocks of 1024 registers. If user wants bigger size memory, it would be necessary to add more blocks. Writing into data memory takes one clock cycle but reading from it can be done instantly(or in relatively shorter time). So we can assume that if we issue address in one clock cycle, we can get the data in the same clock cycle. There is a stack is at the top of data memory and its size is not restricted. Behavioural VHDL description of one instance of data memory is shown in the code below.

Control unit

Fig 7: Control unit FSM

Control unit has four states:

• Fetch: fetches the instructions from instruction memory and loads it in Instruction Register (IR). DPU is IDLE. No Read from data memory.
• Decode: decodes the information in IR. DPU is IDLE. No Read from data memory.
• Execute: if execution on DPU is needed the proper control signals would be provided, otherwise DPU will stay IDLE. Read from data memory performed if needed.
• WriteBack: in case there is a need to write a data into memory it will happen in this stage. All changes in Program Counter(PC) is happening here so all conditional and unconditional branching would be decided in this state. in case the instruction is HALT the PC would be frozen.

VHDL complete versions

• 8-bit Version (17 dec 2014)
• 16-bit Version
• 32-bit Version

Functional Testing

Following machine code program has been made to test functionality of all instructions. The test program doesn’t cover all the cases but run through all the instructions. (at the moment not all the instructions are covered-12% missing)

Load_R0_Dir "00011000" 
OR_A_R  "00000000"
IncA
Sub_A_R "00000000"
NOP
JmpC "00001000"     
NOP
NOP
RRC
RLC
NOP
ClearC
Store_A_Mem  "00010000"
PUSH
SavePC
PUSH
Jump "00010101"
POP
ShiftArithL
DecA
HALT
Load_A_Mem "00010000"
And_A_R "00000000"
JmpZ "00011001"
NOP
ClearZ
Add_A_Mem "00010000"
Sub_A_Mem "00010000"
Add_A_R "00000000"  
Sub_A_Dir "00001100"
FlipA
XOR_A_R "00000000" 
NegA
ShiftArithR
ShiftA_L
ShiftA_R
ClearACC
POP
Add_A_Dir  "00000011"
LoadPC
HALT

Synthesizing and implementation on FPGA

One of the parts of this project is to synthesize 8-bit version of CPU on an FPGA board. "Nexsys 3" board from Digilent has been chosen for implementation. Clock source is controllable via a switch on the board. ClK would be either the 100MHz on-board oscillator or generated signal from one push button (for debugging). The Accumulator value will be displayed on Seven-Segments and the flag values will be displayed on the LEDs.

You need the following files along the CPU VHDL files for synthesis on and implementation on FPGA:

• Top-level Entity: TopLevel.vhd
• Denouncing circuit: Debouncer.vhd
• Seven-segment Decoder: SevenSegment.vhd

Important note: Make sure you set the "FPGA Start-Up Clock" to "JTAG Clock".

The User Constraint File (UCF)

The following is the user constraints file for the project:

NET clk LOC = V10;
NET rst LOC = C4;
NET ClkBttn LOC = D9;
NET ClockSrc LOC = T10;

NET FlagOutput<0> LOC = U16;
NET FlagOutput<1> LOC = V16;
NET FlagOutput<2> LOC = U15;
NET FlagOutput<3> LOC = V15;

NET SevenSeg<6> LOC = T17;
NET SevenSeg<5> LOC = T18;
NET SevenSeg<4> LOC = U17;
NET SevenSeg<3> LOC = U18;
NET SevenSeg<2> LOC = M14;
NET SevenSeg<1> LOC = N14;
NET SevenSeg<0> LOC = L14;

NET AN<3> LOC = P17;
NET AN<2> LOC = P18;
NET AN<1> LOC = N15;
NET AN<0> LOC = N16;

Graphics Card Design

VGA Controller

A simple VGA controller has been designed and synthesised on Nexsys 3 board for the PicoCPU. Controller reads a frame from a video memory and displays it on the monitor. The memory is shared between VGA controller and the graphics processor (coming soon). The user constraint file (UCF) for the vga controller can be found here:

missing ucf file

Graphics processor

Future plans

The following are the future plans for CPU:

• implement barrel shift on acc
• Adding I/O
  • first try would be Input and Output registers
  • wishbone bus maybe?
• Adding interrupts + super user mode (motorla has it MC68K)?
• Pipelining
• Branch prediction
• UART implementation
• implementation of Timers/Counters and peripherals
• Direct Memory Access (DMA)
• Memory management unit (MMU)

Assembler

Python Assembly translator

A simple assembly translator was designed to make debugging process faster. Here you can see 32 bit version of the code:

import re
InstructionOpCode = {

                'Add_A_B':	"000000",
                'Add_A_Mem': 	"000001",
                'Add_A_Dir': 	"000010",
                'Sub_A_B':	"000011",
                'Sub_A_Mem':	"000100",
                'Sub_A_Dir': 	"000101",

                'IncA': 	"000110",
                'DecA':		"000111",

                'ShiftArithR':	"001000",
                'ShiftArithL':	"001001",
                'ShiftA_R':	"001010",
                'ShiftA_L':	"001011",
                'RRC':	  	"001100",
                'RLC':		"001101",

                'And_A_B':	"001110",
                'OR_A_B':	"001111",
                'XOR_A_B':	"010000",
                'FlipA':	"010001",
                'NegA':		"010010 ",

                'Jump':		"010011",
                'JmpZ':		"010100",
                'JmpOV':	"010101",
                'JmpC':		"010110",
                'Jmp_rel':	"010111",
                'JMPEQ':	"011000",

                'ClearZ':	"011001",
                'ClearOV':	"011010 ",
                'ClearC':	"011011",
                'ClearACC':	"011100",

                'LoadPC': 	"011101",
                'SavePC':	"011110",

                'Load_A_Mem':	"011111",
                'Store_A_Mem':	"100000",
                'Load_B_Dir':	"100001",
                'Load_B_Mem':	"100010",

                'Load_A_B':	"100011",
                'Load_B_A':	"100100",
                'Load_Ind_A ':	"100101",

                'PUSH':		"111100",
                'POP':		"111101",
                'NOP':		"111110",
                'HALT':		"111111",

}
AssemblyFile = open('Assembly.txt', 'r+')
MachineCodeFile = open('MachineCode.txt', 'w')
counter=0
for line in AssemblyFile:

    for key in InstructionOpCode:
        if key in line:
            operand= "00000000"
            if "Mem" in line:
                operand = re.findall(r'\d+',line)[0]
            elif "Jmp" in line:
                operand = re.findall(r'\d+',line)[0]
            elif "Dir" in line:
                operand = re.findall(r'\d+',line)[0]
            operand = "00000000"+"00000000"+"00000000"+ operand
            MachineCodeFile.write(str(counter)+ " =>   "+ "\"00"+InstructionOpCode[key]+operand+'\",'+'\n')
            counter +=1

MachineCodeFile.close()
AssemblyFile.close()

Java Assembler

This Assembler is wrote by Karl Janson as a project during system modelling course. You can find the information about how to use it in the User Manual.

Downloads

• Executable File:
• The Assembler code: File:picoAssembler.zip
• Assembler Instructions File: File:intructions.txt

Note: Codes and User Manual for the assembler are placed in the Public Domain with the authorization of its author, Karl Janson.

Compiler