CDS TT

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Purpose of this tutorial is how to export edif out of Cadence Virtuoso

NB! To first import your design into Virtuoso, use this tutorial.

Setting up the environment

following commands are all in commandline

  • move to your design folder noc_synth
  • I have a separate folder for virtuoso, to keep folder structure more clear.
  • using command 'cad', choose option '1' to initialize environment variables for Cadence tools.
Setting up working environment

Bringing up Virtuoso

  • If you have never invoked following command in your current design folder, then there is a great possibility that you have not imported your design yet and you should follow this tutorial first.
ams_cds -64 -tech c18a6 -add CORELIB -add IOLIB_6AM -add GATES_ANA
  • If you are sure that you have invoked previously that command and you have design imported, you can bring up Virtuoso with following command.
ams_cds

Exporting edif

For exporting previously imported design we need to only use this window.

Main Virtuoso window

From that window search under 'File' menu 'export' and click 'EDIF200'

Exporting EDIF

This should bring up a following window

EDIF export window

First step is to 'Browse' for your design.

EDIF export window

Find your design by selecting your designs 'Library', then a 'cell' that you want to export and finally 'schematic'. Close the window just by clicking 'Close' and your design should be included now in the Export window.

Setting EDIF export options

Final steps before exporting:

  • Set External Library to 'CORELIB'
  • Give your design a name by filling Design Name
  • Give Output File name
  • Set Output format to 'Netlist'
  • Select 'Expand All Objects Except Ports'
  • Set Netlist Transition Mode to 'Flat'

When these options have been set, you can push OK to export your design in edif.

NB! After Clicking OK there should appear a prompt for displaying the export log. Check it to make sure that 'Writing cell cds_thru' is NOT present there. If it is, then you should re-visit importing your design. This line generates 'INOUT' ports in the EDIF and TT cannot understand them.