Sharjeel
Contents
Sharjeel Imtiaz
About
Sharjeel Imtiaz is a Ph.D. researcher in Information Technology with a focus on hardware design and hardware security. His research interests include secure processor architectures, hardware verification, and design automation.
This page is intended for documenting laboratory work, experiments, and research-related activities.
Affiliation
- Ph.D. Researcher, Tallinn University of Technology (TalTech), Estonia
Research Interests
- Secure processor design
- Hardware design and verification
- Hardware security
- RISC-V architectures
- AI accelerators
- Electronic Design Automation (EDA)
Skills
- Hardware Description Languages: Verilog, SystemVerilog, VHDL, Chisel
- Verification: Formal verification, assertions, simulation
- EDA Tools: Cadence JasperGold, Xilinx Vivado, QuestaSim, GTKWave, Cocotb
- Programming: Python, C/C++
- Scripting: Python, Tcl, Bash, MATLAB
- Other: Linux, Git, LaTeX
Profiles
- GitHub: https://github.com/Sharjeelimtiaz27
- LinkedIn: https://www.linkedin.com/in/sharjeel-imtiaz-1b1a9a117/
Publications
- Imtiaz, Sharjeel (2025). Application of Functional Verification Techniques in Hardware Trust. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).
- Imtiaz, Sharjeel et al. (2025). Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study. IEEE International Symposium on Circuits and Systems (ISCAS).
Course Highlights
This section documents courses where I am involved as a Lab Assistant, including lab materials, experiments, and teaching-related resources.
IAS0630 – Hardware Security (Spring 2026)
Role: Lab Assistant Institution: Tallinn University of Technology (TalTech)
Course Overview
This course focuses on hardware security concepts, threats, and countermeasures at different abstraction levels.
IAS0430 – Microprocessor Systems (2025)
Role: Lab Assistant Institution: Tallinn University of Technology (TalTech)
Course Overview
This course covers microprocessor architectures, interfacing, and low-level system design.
