Difference between revisions of "Glossary"

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{|
 
{|
−
| Hard core || Physical manifestations of the IP design
+
| ACM || Adaptive Computing Machine
 +
|-
 +
| ASIC || Application Specific Integrated Circuit
 +
|-
 +
| ASM || Abstract State Machines
 +
|-
 +
| EDA || Electronic Design Automation
 +
|-
 +
| CLB || Configurable Logic Block (of FPGA)
 
|-
 
|-
 
| CSP || Communicating Sequential Processes  
 
| CSP || Communicating Sequential Processes  
 +
|-
 +
| DSM || Deep SubMicron
 +
|-
 +
| DSP || Digital Signal Processor
 
|-
 
|-
 
| Firm core || (or semi-hard core) IP-s carrying placement data but configurable for various applications  
 
| Firm core || (or semi-hard core) IP-s carrying placement data but configurable for various applications  
Line 8: Line 20:
 
| ESL || Electronic System Level  
 
| ESL || Electronic System Level  
 
|-
 
|-
−
| CLB || Configurable Logic Block (of FPGA)
+
| FPGA || Field Programmable Gate Array
 +
|-
 +
| Hard core || Physical manifestations of the IP design
 
|-
 
|-
 
| HLS || High Level Synthesis  
 
| HLS || High Level Synthesis  
 +
|-
 +
| HSCO || Hardware-Software Co-Design
 
|-
 
|-
 
| IEEE || Institute of Electrical and Electronic Engineers, Inc.  
 
| IEEE || Institute of Electrical and Electronic Engineers, Inc.  
 
|-
 
|-
 
| IP (core) || Intellectual Property (core), synonymous with Virtual Component (VC)  
 
| IP (core) || Intellectual Property (core), synonymous with Virtual Component (VC)  
−
|-
 
−
| VHDL || Very high speed Hardware Description Language
 
−
|-
 
−
| VITAL || VHDL Initiative Toward ASIC Libraries
 
−
|-
 
−
| VLIW || Very Long Instruction Word (processor)
 
−
|-
 
−
| VLSI || Very Large Scale Integration (Integrated Circuit)
 
 
|-
 
|-
 
| ISA (model) || Instruction Set Architecture (model)  
 
| ISA (model) || Instruction Set Architecture (model)  
 
|-
 
|-
−
| ASIC || Application Specific Integrated Circuit
+
| LRM || Language Reference Manual
 
|-
 
|-
−
| ACM || Adaptive Computing Machine
+
| netlist || A list of logic gates and associated interconnections making up an integrated circuit
 
|-
 
|-
−
| LRM || Language Reference Manual
+
| NoC || Network-on-Chip
 
|-
 
|-
 
| PCB || Printed Circuit Board  
 
| PCB || Printed Circuit Board  
 
|-
 
|-
−
| netlist || A list of logic gates and associated interconnections making up an integrated circuit
+
| RTL || Register-Transfer Level
 
|-
 
|-
−
| SoC || System-on-Chip
+
| SDL || Specification and Description Language, standardized by ITU (International Telecommunication Union)
 
|-
 
|-
−
| SW || Software
+
| SLB || System Level Block
 
|-
 
|-
 
| Soft core || IP presented as a netlist or HDL code  
 
| Soft core || IP presented as a netlist or HDL code  
 
|-
 
|-
−
| DSM || Deep SubMicron
+
| SoC || System-on-Chip
 
|-
 
|-
−
| DSP || Digital Signal Processor
+
| SW || Software
 +
|-
 +
| Synopsys VSS || Synopsys VHDL System Simulator
 
|-
 
|-
 
| HW || Hardware  
 
| HW || Hardware  
Line 50: Line 60:
 
| UML || Universal Modeling Language  
 
| UML || Universal Modeling Language  
 
|-
 
|-
−
| VSIA || Virtual Socket Initiative Alliance
+
| VHDL || Very high speed Hardware Description Language
 
|-
 
|-
−
| RTL || Register-Transfer Level
+
| VITAL || VHDL Initiative Toward ASIC Libraries
 
|-
 
|-
−
| CDFG || Control Data Flow Graph
+
| VLIW || Very Long Instruction Word (processor)
 
|-
 
|-
−
| NoC || Network-on-Chip
+
| VLSI || Very Large Scale Integration (Integrated Circuit)
 
|-
 
|-
−
| SDL || Specification and Description Language, standardized by ITU (International Telecommunication Union)
+
| VSIA || Virtual Socket Initiative Alliance
 
|-
 
|-
−
| HSCO || Hardware-Software Co-Design
+
| CDFG || Control Data Flow Graph
−
|-
+
−
| SLB || System Level Block
+
−
|-
+
−
| ASM || Abstract State Machines
+
−
|-
+
−
| EDA || Electronic Design Automation
+
 
|-
 
|-
 
| XPP || eXtreme Processing Platform of PACT  
 
| XPP || eXtreme Processing Platform of PACT  
−
|-
 
−
| FPGA || Field Programmable Gate Array
 
 
|}
 
|}

Revision as of 21:59, 20 April 2010

ACM Adaptive Computing Machine
ASIC Application Specific Integrated Circuit
ASM Abstract State Machines
EDA Electronic Design Automation
CLB Configurable Logic Block (of FPGA)
CSP Communicating Sequential Processes
DSM Deep SubMicron
DSP Digital Signal Processor
Firm core (or semi-hard core) IP-s carrying placement data but configurable for various applications
ESL Electronic System Level
FPGA Field Programmable Gate Array
Hard core Physical manifestations of the IP design
HLS High Level Synthesis
HSCO Hardware-Software Co-Design
IEEE Institute of Electrical and Electronic Engineers, Inc.
IP (core) Intellectual Property (core), synonymous with Virtual Component (VC)
ISA (model) Instruction Set Architecture (model)
LRM Language Reference Manual
netlist A list of logic gates and associated interconnections making up an integrated circuit
NoC Network-on-Chip
PCB Printed Circuit Board
RTL Register-Transfer Level
SDL Specification and Description Language, standardized by ITU (International Telecommunication Union)
SLB System Level Block
Soft core IP presented as a netlist or HDL code
SoC System-on-Chip
SW Software
Synopsys VSS Synopsys VHDL System Simulator
HW Hardware
UML Universal Modeling Language
VHDL Very high speed Hardware Description Language
VITAL VHDL Initiative Toward ASIC Libraries
VLIW Very Long Instruction Word (processor)
VLSI Very Large Scale Integration (Integrated Circuit)
VSIA Virtual Socket Initiative Alliance
CDFG Control Data Flow Graph
XPP eXtreme Processing Platform of PACT
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