Difference between revisions of "Glossary"

From ATI public wiki
Jump to: navigation, search
 
(8 intermediate revisions by the same user not shown)
Line 1: Line 1:
 
{|
 
{|
−
| Hard core || Physical manifestations of the IP design
+
| ACM || Adaptive Computing Machine
 +
|-
 +
| ASIC || Application Specific Integrated Circuit
 +
|-
 +
| ASM || Abstract State Machines
 +
|-
 +
| BFM  || Bus Functional Model
 +
|-
 +
| CDFG || Control Data Flow Graph
 +
|-
 +
| CLB || Configurable Logic Block (of FPGA)
 
|-
 
|-
 
| CSP || Communicating Sequential Processes  
 
| CSP || Communicating Sequential Processes  
 
|-
 
|-
−
| Firm core || (or semi-hard core) IP-s carrying placement data but configurable for various applications
+
| DSM || Deep SubMicron
 +
|-
 +
| DSP || Digital Signal Processor
 +
|-
 +
| EDA || Electronic Design Automation
 
|-
 
|-
 
| ESL || Electronic System Level  
 
| ESL || Electronic System Level  
 
|-
 
|-
−
| CLB || Configurable Logic Block (of FPGA)  
+
| Firm core || (or semi-hard core) IP-s carrying placement data but configurable for various applications
 +
|-
 +
| FPGA || Field Programmable Gate Array
 +
|-
 +
| Hard core || Physical manifestations of the IP design
 
|-
 
|-
 
| HLS || High Level Synthesis  
 
| HLS || High Level Synthesis  
 
|-
 
|-
−
| IEEE || Institute of Electrical and Electronic Engineers, Inc.
+
| HSCO || Hardware-Software Co-Design
 
|-
 
|-
−
| IP (core) || Intellectual Property (core), synonymous with Virtual Component (VC)
+
| HW || Hardware
 
|-
 
|-
−
| VHDL || Very high speed Hardware Description Language
+
| ICE  || In Circuit Emulator
 
|-
 
|-
−
| VLIW || Very Long Instruction Word (processor)
+
| IEEE || Institute of Electrical and Electronic Engineers, Inc.
 
|-
 
|-
−
| VLSI || Very Large Scale Integration (Integrated Circuit)  
+
| IP (core) || Intellectual Property (core), synonymous with Virtual Component (VC)
 +
|-
 +
| IPC  || Inter Process Communication
 
|-
 
|-
 
| ISA (model) || Instruction Set Architecture (model)  
 
| ISA (model) || Instruction Set Architecture (model)  
 
|-
 
|-
−
| ASIC || Application Specific Integrated Circuit
+
| LRM || Language Reference Manual
 
|-
 
|-
−
| ACM || Adaptive Computing Machine
+
| netlist || A list of logic gates and associated interconnections making up an integrated circuit
 
|-
 
|-
−
| LRM || Language Reference Manual
+
| NoC || Network-on-Chip
 
|-
 
|-
 
| PCB || Printed Circuit Board  
 
| PCB || Printed Circuit Board  
 
|-
 
|-
−
| netlist || A list of logic gates and associated interconnections making up an integrated circuit
+
| RTL || Register-Transfer Level
 
|-
 
|-
−
| SoC || System-on-Chip
+
| SDL || Specification and Description Language, standardized by ITU (International Telecommunication Union)
 
|-
 
|-
−
| SW || Software
+
| SLB || System Level Block
 +
|-
 +
| SoC || System-on-Chip
 
|-
 
|-
 
| Soft core || IP presented as a netlist or HDL code  
 
| Soft core || IP presented as a netlist or HDL code  
 
|-
 
|-
−
| DSM || Deep SubMicron
+
| SW || Software
 
|-
 
|-
−
| DSP || Digital Signal Processor
+
| Synopsys VCS || Synopsys Verilog Simulator
 
|-
 
|-
−
| HW || Hardware
+
| Synopsys VSS || Synopsys VHDL System Simulator
 +
|-
 +
| UCF  || User Constraint File
 
|-
 
|-
 
| UML || Universal Modeling Language  
 
| UML || Universal Modeling Language  
 
|-
 
|-
−
| VSIA || Virtual Socket Initiative Alliance
+
| VCI  || VHDL-C Interface
 
|-
 
|-
−
| RTL || Register-Transfer Level
+
| VHDL || Very high speed Hardware Description Language
 
|-
 
|-
−
| CDFG || Control Data Flow Graph
+
| VITAL || VHDL Initiative Toward ASIC Libraries
 
|-
 
|-
−
| NoC || Network-on-Chip
+
| VLIW || Very Long Instruction Word (processor)
 
|-
 
|-
−
| SDL || Specification and Description Language, standardized by ITU (International Telecommunication Union)  
+
| VLSI || Very Large Scale Integration (Integrated Circuit)  
 
|-
 
|-
−
| HSCO || Hardware-Software Co-Design
+
| VSIA || Virtual Socket Initiative Alliance
−
|-
+
−
| SLB || System Level Block
+
−
|-
+
−
| ASM || Abstract State Machines
+
−
|-
+
−
| EDA || Electronic Design Automation
+
 
|-
 
|-
 
| XPP || eXtreme Processing Platform of PACT  
 
| XPP || eXtreme Processing Platform of PACT  
−
|-
 
−
| FPGA || Field Programmable Gate Array
 
 
|}
 
|}

Latest revision as of 22:52, 20 April 2010

ACM Adaptive Computing Machine
ASIC Application Specific Integrated Circuit
ASM Abstract State Machines
BFM Bus Functional Model
CDFG Control Data Flow Graph
CLB Configurable Logic Block (of FPGA)
CSP Communicating Sequential Processes
DSM Deep SubMicron
DSP Digital Signal Processor
EDA Electronic Design Automation
ESL Electronic System Level
Firm core (or semi-hard core) IP-s carrying placement data but configurable for various applications
FPGA Field Programmable Gate Array
Hard core Physical manifestations of the IP design
HLS High Level Synthesis
HSCO Hardware-Software Co-Design
HW Hardware
ICE In Circuit Emulator
IEEE Institute of Electrical and Electronic Engineers, Inc.
IP (core) Intellectual Property (core), synonymous with Virtual Component (VC)
IPC Inter Process Communication
ISA (model) Instruction Set Architecture (model)
LRM Language Reference Manual
netlist A list of logic gates and associated interconnections making up an integrated circuit
NoC Network-on-Chip
PCB Printed Circuit Board
RTL Register-Transfer Level
SDL Specification and Description Language, standardized by ITU (International Telecommunication Union)
SLB System Level Block
SoC System-on-Chip
Soft core IP presented as a netlist or HDL code
SW Software
Synopsys VCS Synopsys Verilog Simulator
Synopsys VSS Synopsys VHDL System Simulator
UCF User Constraint File
UML Universal Modeling Language
VCI VHDL-C Interface
VHDL Very high speed Hardware Description Language
VITAL VHDL Initiative Toward ASIC Libraries
VLIW Very Long Instruction Word (processor)
VLSI Very Large Scale Integration (Integrated Circuit)
VSIA Virtual Socket Initiative Alliance
XPP eXtreme Processing Platform of PACT
Retrieved from "https://strudel.pld.ttu.ee/wiki/e/index.php?title=Glossary&oldid=911"