Difference between revisions of "Pipelined Version"
From ATI public wiki
m |
m |
||
| (One intermediate revision by the same user not shown) | |||
| Line 1: | Line 1: | ||
[[File:PipelinedPicoCPU.jpg|400px|thumb|right|alt= text| Fig 1: System Block Diagram]] | [[File:PipelinedPicoCPU.jpg|400px|thumb|right|alt= text| Fig 1: System Block Diagram]] | ||
| − | [[File:DifferentPipesState.jpg| | + | [[File:DifferentPipesState.jpg|500px|thumb|right|alt= text| Fig 2: Different Pipes States]] |
| − | + | ||
| + | The Building Components are the same as the non-pipeline version. The only major difference is the control unit | ||
| + | which has the pipes. | ||
| + | |||
===Current versions (VHDL)=== | ===Current versions (VHDL)=== | ||
* 28 Feb 2015: [[:File:PicoPipe_8bit.zip|8-bit pipelined]] | * 28 Feb 2015: [[:File:PicoPipe_8bit.zip|8-bit pipelined]] | ||
Latest revision as of 19:50, 28 February 2015
The Building Components are the same as the non-pipeline version. The only major difference is the control unit which has the pipes.
Current versions (VHDL)
- 28 Feb 2015: 8-bit pipelined
Future plans
- Pipelining PC and SP
- Adding Branch prediction etc.
- Still needs NOPs inserted after JMPs and HALT (To prevent data hazards.)
