Revision as of 20:57, 29 January 2017

Introduction

Welcome to SoC design wiki. We started this series of labs/projects from 2014 and we are upgrading and fixing problems every year to make it better.

Learning Objectives

By completion of this SoC Design labs, you should be able to:

Labs Requirements

For this labs we assume that you have passed the following courses:

• IAY0600: Digital Systems Design
• IAY0330: Embedded Systems

So that you are familiar with digital systems (you should be familiar with High Level Description Languages like VHDL or Verilog (our main focus is on VHDL but if you know Verilog, its also ok!)) and Embedded Systems.

Labs Regulations

Current Lab Results

	You can view you current lab results and statistics here

Contact Us

In case of any questions, please contact us:

	• Karl Janson
	• Siavoosh Payandeh Azad

Rules and Regulations

Please read the following page before you start the course:

Timing and plans

Please note that the project ends at the end of semester and will not be extended.

Writing code

We would like to re-use your codes later on so keep these things in mind:

• Use comments in your code. Even you, as the programmer, who wrote the code, will otherwise not understand your code after a while.
• Write a a proper doc-string for the functions. It makes the life of you and others a lot easier.
• Use meaningful variable names. The purpose of a variable with the name "counterMaxValue" is much easier to understand that the same variable with the name "cMNum", for example.

Documentation

• All documentation goes to wiki, messy and unorganized documentations are not acceptable.
• If you have a problem with some of the labs, check the Labs known Issues page before asking for help. Sometimes the issue is already solved.
• If it is not solved yet and you find a workaround for it, please document it in Labs known Issues. This way others can don't have to invent the wheel again.

Lab Tutorials

The following is the test lab for the first week of the semester. :) Enjoy!

• Test Lab

Here you can find lab manuals for the tutorials:

• Lab 1: Kernel Driver
• Lab 2: Building custom SoC on ZedBoard
• Lab 3: Custom IP creation
• Lab 4: Setup 1 board system for the lab

Labs additional readings

Additional reading and more information about the labs can be found here:

General documents

• Creating a new project in Vivado
• Basic information about Linux
• Using ZedBoard

Lab specific documents

• Lab1 additional material
• Lab2 additional material
• Lab3 additional material
• Lab4 additional material

Labs known issues

Please add related issues to each lab under the Labs known Issues page.

Tutorial Labs Archive

• 2015 Tutorials
• 2014 Tutorials

Audio Mixer Project

Project Description

Design project is defined in each round for System on Chip design(IAY0550) students with the aim of providing them with real world experience of working on a SoC project, teamwork and project management. This wiki will serve as a platform for students to pass-on their designs and documents to students in the next round of course. Full description of the project can be found on the Project Description page

• Project Description page.

Git

The project code should be stored in git. Every component of the project should be uploaded as a separate branch.

There exists a dedicated Github repository for the course, that can be accessed here: [1]

Team Organization

The following page is for clear and transparent team organization for design project:

• Team Organization Spring 2014
• Team Organization Spring 2015

Design project

• Old project archive (2014/2015)