Difference between revisions of "Main Page"
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==Introduction== | ==Introduction== | ||
| − | Welcome to SoC design | + | Welcome to teh wiki for the SoC design! We started this series of labs/projects in 2014 and we are upgrading and fixing problems every year to make it better. |
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===Learning Objectives=== | ===Learning Objectives=== | ||
| − | + | After the completion of the labs, you are able to: | |
{| | {| | ||
|style="vertical-align:top;"| | |style="vertical-align:top;"| | ||
'''Tutorials''': | '''Tutorials''': | ||
| − | # | + | # Make Linux kernel drivers: Write a simple kernel driver for controlling a simple IP (intellectual property) on ZedBoard. |
| − | # | + | # Build custom SoC (System-on-Chip) on ZedBoard: |
| − | #* | + | #* Create a simple SoC with Vivado from existing IPs |
| − | #* | + | #* Build a custom embedded Linux system to run on the SoC |
| − | #*Using custom kernel drivers to control the IPs in the SoC | + | #* Using custom kernel drivers to control the IPs in the SoC |
| − | # | + | # Create custom IPs: |
| − | #*Development of simple custom IP | + | #* Development of simple custom IP from VHDL code |
| − | #* | + | #* Integrate the IP into the SoC using AXI bus |
| − | #* | + | #* Control the IP from Linux using custom driver |
| − | # | + | # Build a simple audio processor system |
| − | #*Complex system integration | + | #* Complex system integration |
| − | #*Preparation for project | + | #* Preparation for course project |
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|style="vertical-align:top;"| | |style="vertical-align:top;"| | ||
'''Project''': | '''Project''': | ||
| − | *Component reuse and system improvement | + | * Component reuse and system improvement |
| − | *Functional test and analysis | + | * Functional test and analysis |
| − | * | + | * Working in a team |
|} | |} | ||
Revision as of 14:57, 2 September 2019
Introduction
Welcome to teh wiki for the SoC design! We started this series of labs/projects in 2014 and we are upgrading and fixing problems every year to make it better.
Learning Objectives
After the completion of the labs, you are able to:
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Tutorials:
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Project:
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Labs Requirements
For these labs we assume that you have passed the following courses:
- IAY0600: Digital Systems Design
- IAY0330: Embedded Systems
So that you are familiar with digital systems and Embedded Systems. You should be familiar with High Level Description Languages like VHDL or Verilog (our main focus is on VHDL but if you know Verilog, it is also ok!).
Lab Organization
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Important dates
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Lab grading policy
In order to pass the course, you have to get a positive result in both the project and the exam. You cannot finish the project without passing all tutorial labs! |
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Current Lab Results
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You can view you current lab results and statistics here |
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Contact Us
In case of any questions, please contact us:
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• Karl Janson |
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| • Madis Kerner |
Rules and Regulations
Please read the following page before you start the course:
Timing and Plans
Please note that the project ends at the end of semester and will not be extended.
General Rules
- Unplugging any cables from the lab computers is NOT ALLOWED! If you use your own computer, please use Wi-Fi.
- It is OK to discuss your code with co-students during the labs.
- Copying co-student's code is not OK! You need to write it yourself.
- You must understand the code you write! We will check everyone.
Writing Code
We would like to re-use your code later on so keep these things in mind:
- Use comments in your code. Even you, as the programmer, who wrote the code, will otherwise not understand your code after a while.
- Write a proper doc-string for the functions. It makes the life of you and others a lot easier.
- Use meaningful variable names. The purpose of a variable with the name "counterMaxValue" is much easier to understand that the same variable with the name "cMNum", for example.
In Case of Problems
Please use the following methods in the following order for solving your issues:
- Check the current lab's additional materials.
- Re-read the lab manual to make sure you did not miss anything.
- Google your problems
- Ask the lab assistants for help.
NOTE: In case you find a problem with the documentation, please tell the assistants. Then we can fix the problem and everyone will be happy :)
Lab Tasks
Lab Tutorials
Here you can find lab manuals for the tutorials:
- Lab 1: Kernel Driver
- Lab 2: Building custom SoC on ZedBoard
- Lab 3: Custom IP creation
- Lab 4: Setup 1 board system for the lab
Labs additional readings
Additional reading and more information about the labs can be found here:
General documents
Lab specific documents
Using Own Computer for the Labs
If you plan to use your own computer, please refer to the Using Own Computer page.
Tutorial Labs Archive
Audio Mixer Project
Project Description
Design project is defined in each round for System on Chip design(IAY0550) students with the aim of providing them with real world experience of working on a SoC project, teamwork and project management. This wiki will serve as a platform for students to pass-on their designs and documents to students in the next round of course. Full description of the project can be found on the Project Description page
- Project Description page.
Git
The project code should be stored in git. Every component of the project should be uploaded as a separate branch.
There exists a dedicated Github repository for the course, that can be accessed here: [1]
Team Organization
The following page is for clear and transparent team organization for design project:
