Difference between revisions of "Main Page"
From SoC Design Wiki
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| − | + | [[File:Logo_SoC.png|300px|right]] | |
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| − | + | ==Introduction== | |
| + | Welcome to SoC design wiki. We started this series of labs/projects from 2014 and we are upgrading and fixing problems every year to make it better. | ||
| + | ===Learning Objectives=== | ||
| + | By completion of this SoC Design labs, you should be able to: | ||
| − | + | {| | |
| − | + | |style="vertical-align:top;"| | |
| − | + | '''Tutorials''': | |
| − | + | #Kernel Driver: How to write a simple kernel driver and use it to control a simple IP on ZedBoard. | |
| − | + | #Building custom SoC on ZedBoard: | |
| − | + | #*Creation of simple SoC with Vivado from existing IPs | |
| + | #*Building a custom embedded Linux system to be run on the SoC | ||
| + | #*Using custom kernel drivers to control the IPs in the SoC | ||
| + | #Custom IP creation: | ||
| + | #*Development of simple custom IP | ||
| + | #*Integrating IP into the SoC using AXI bus | ||
| + | #*Controlling the IP from Linux using custom driver | ||
| + | #Setup 1 board system for the lab | ||
| + | #*Complex system integration | ||
| + | #*Preparation for project | ||
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| − | + | ||
| − | ==Labs | + | |style="vertical-align:top;"| |
| − | We keep the | + | '''Project''': |
| + | *Component reuse and system improvement | ||
| + | *Functional test and analysis | ||
| + | *Work in a team | ||
| + | |} | ||
| + | |||
| + | ===Labs Requirements=== | ||
| + | For these labs we assume that you have passed the following courses: | ||
| + | * IAY0600: Digital Systems Design | ||
| + | * IAY0330: Embedded Systems | ||
| + | So that you are familiar with digital systems and Embedded Systems. You should be familiar with High Level Description Languages like VHDL or Verilog (our main focus is on VHDL but if you know Verilog, it is also ok!). | ||
| + | |||
| + | ===Lab Organization=== | ||
| + | {| | ||
| + | |style="vertical-align:top;"| | ||
| + | '''Important dates''' | ||
| + | |||
| + | * <span style="color:#FF0000">'''Week 1, week 2, week 3''':</span> Lab 1 | ||
| + | * <span style="color:#FF0000">'''Week 4''':</span> Lab 2 | ||
| + | * <span style="color:#FF0000">'''Week 5, week 6, week 7, week 8''':</span> Lab 3 | ||
| + | * <span style="color:#FF0000">'''Week 9, week 10''':</span> Lab 4 | ||
| + | * <span style="color:#FF0000">'''Week 11''':</span> Backup time | ||
| + | * <span style="color:#FF0000">'''End of week 15''':</span> Project Deadline | ||
| + | |||
| + | |style="vertical-align:top;"| | ||
| + | | ||
| + | | ||
| + | | ||
| + | | ||
| + | |||
| + | |style="vertical-align:top;"| | ||
| + | '''Lab grading policy''' | ||
| + | * Basic Tutorials (Pass/Fail - prerequisite for project) (30%) (this is prerequisite for project) | ||
| + | * Project (20%) (prerequisite for Exam) | ||
| + | * Final Course Examination (50%) | ||
| + | |||
| + | |style="vertical-align:top;"| | ||
| + | | ||
| + | | ||
| + | | ||
| + | | ||
| + | |style="vertical-align:top;"| | ||
| + | [[File:Grading.png|300px]] | ||
| + | |||
| + | |} | ||
| + | |||
| + | ===Current Lab Results=== | ||
| + | {| | ||
| + | ! rowspan="2" | [[File:statistics-512.png|70px|left]] | ||
| + | ! style="text-align:left;" | You can view you current lab results and statistics [https://docs.google.com/spreadsheets/d/1kVySrAtkDZ8vfu33Hx0nmoimQDt9LwRKIhNigxA1oAU/pubhtml?gid=1477271030&single=true '''here'''] | ||
| + | |} | ||
| + | |||
| + | ===Contact Us=== | ||
| + | In case of any questions, please contact us: | ||
| + | |||
| + | {| | ||
| + | ! rowspan="2" | [[File:redphone.png|70px|left]] | ||
| + | | style="text-align:left;" | '''• [http://ati.ttu.ee/socdesign/index.php/User:Kjans Karl Janson]''' | ||
| + | |} | ||
| + | |||
| + | ==Rules and Regulations== | ||
| + | <span style="color:red"> '''Please read the following page before you start the course:''' </span> | ||
| + | |||
| + | ===Timing and Plans=== | ||
| + | '''Please note that the project ends at the end of semester and will not be extended.''' | ||
| + | |||
| + | ===General Rules=== | ||
| + | * <span style="color:red">'''Un-pluging any cables is from the lab computers is NOT ALLOWED!'''</span> If you use your own computer, please use Wi-Fi. | ||
| + | * It is '''OK''' to discuss your code with co-students during the labs. | ||
| + | * Copying co-student's code '''is not''' OK! You need to write it yourself. | ||
| + | * You '''must''' understand the code you write! We will check everyone. | ||
| + | |||
| + | ===Writing Code=== | ||
| + | We would like to re-use your codes later on so keep these things in mind: | ||
| + | * '''Use comments in your code.''' Even you, as the programmer, who wrote the code, will otherwise not understand your code after a while. | ||
| + | * '''Write a a proper doc-string for the functions.''' It makes the life of you and others a lot easier. | ||
| + | * '''Use meaningful variable names.''' The purpose of a variable with the name "counterMaxValue" is much easier to understand that the same variable with the name "cMNum", for example. | ||
| + | |||
| + | ===In Case of Problems=== | ||
| + | '''Please use the following methods in the following order for solving your issues:''' | ||
| + | |||
| + | # Check the current lab's additional materials. | ||
| + | # Re-read the lab manual to make sure you did not miss anything. | ||
| + | # Google your problems | ||
| + | # Ask the lab assistants for help. | ||
| + | |||
| + | '''NOTE:''' In case you find a problem with the documentation, please tell the assitants. Then we can fix the problem and everyone will be happy :) | ||
| + | |||
| + | <!-- *[[Rules and Regulations]] --> | ||
| + | |||
| + | == Lab Tasks == | ||
| + | ===Lab Tutorials=== | ||
| + | Here you can find lab manuals for the tutorials: | ||
| + | *[[Lab 1|Lab 1: Kernel Driver]] | ||
| + | *[[Lab 2|Lab 2: Building custom SoC on ZedBoard]] | ||
| + | *[[Lab 3|Lab 3: Custom IP creation]] | ||
| + | *[[Lab 4|Lab 4: Setup 1 board system for the lab]] | ||
| + | |||
| + | ===Labs additional readings=== | ||
| + | |||
| + | Additional reading and more information about the labs can be found here: | ||
| + | ====General documents==== | ||
| + | *[[Creating a new project in Vivado]] | ||
| + | *[[Basic information about Linux]] | ||
| + | *[[Using ZedBoard]] | ||
| + | |||
| + | ====Lab specific documents==== | ||
*[[Lab1 additional material]] | *[[Lab1 additional material]] | ||
*[[Lab2 additional material]] | *[[Lab2 additional material]] | ||
*[[Lab3 additional material]] | *[[Lab3 additional material]] | ||
| + | *[[Lab4 additional material]] | ||
| + | |||
| + | ===Using Own Computer for the Labs=== | ||
| + | If you plan to use your own computer, please refer to the [[Using Own Computer]] page. | ||
| + | |||
| + | ===Tutorial Labs Archive === | ||
| + | *[[2016 Tutorials]] | ||
| + | *[[2015 Tutorials]] | ||
| + | *[[2014 Tutorials]] | ||
| + | |||
| + | =Audio Mixer Project= | ||
| + | ==Project Description== | ||
| + | [[File:mixer.jpg|300px|right]] | ||
| + | [[File:Zedboard_icon.png|53px|left]] | ||
| + | Design project is defined in each round for System on Chip design(IAY0550) students with the aim of providing them with real world experience of working on a SoC project, teamwork and project management. This wiki will serve as a platform for students to pass-on their designs and documents to students in the next round of course. Full description of the project can be found on the Project Description page | ||
| + | * '''[[Project Description]] page'''. | ||
| + | |||
| + | ==Git== | ||
| + | [[File:github.png|43px|left]] | ||
| + | The project code should be stored in git. Every component of the project should be uploaded as a separate branch. | ||
| + | |||
| + | There exists a dedicated Github repository for the course, that can be accessed here: [https://github.com/karljans/SoC_Design] | ||
| + | |||
| + | ==Team Organization== | ||
| + | The following page is for clear and transparent team organization for design project: | ||
| + | *[[Team Organization Spring 2014]] | ||
| + | *[[Team Organization Spring 2015]] | ||
| + | |||
| + | ==Design project== | ||
| − | + | * [[Old project archive (2014/2015)]] | |
| − | + | ||
Revision as of 01:59, 14 February 2017
Introduction
Welcome to SoC design wiki. We started this series of labs/projects from 2014 and we are upgrading and fixing problems every year to make it better.
Learning Objectives
By completion of this SoC Design labs, you should be able to:
|
Tutorials:
|
|
Project:
|
Labs Requirements
For these labs we assume that you have passed the following courses:
- IAY0600: Digital Systems Design
- IAY0330: Embedded Systems
So that you are familiar with digital systems and Embedded Systems. You should be familiar with High Level Description Languages like VHDL or Verilog (our main focus is on VHDL but if you know Verilog, it is also ok!).
Lab Organization
|
Important dates
|
|
Lab grading policy
|
|
|
Current Lab Results
 |
You can view you current lab results and statistics here |
|---|
Contact Us
In case of any questions, please contact us:
 |
• Karl Janson |
|---|
Rules and Regulations
Please read the following page before you start the course:
Timing and Plans
Please note that the project ends at the end of semester and will not be extended.
General Rules
- Un-pluging any cables is from the lab computers is NOT ALLOWED! If you use your own computer, please use Wi-Fi.
- It is OK to discuss your code with co-students during the labs.
- Copying co-student's code is not OK! You need to write it yourself.
- You must understand the code you write! We will check everyone.
Writing Code
We would like to re-use your codes later on so keep these things in mind:
- Use comments in your code. Even you, as the programmer, who wrote the code, will otherwise not understand your code after a while.
- Write a a proper doc-string for the functions. It makes the life of you and others a lot easier.
- Use meaningful variable names. The purpose of a variable with the name "counterMaxValue" is much easier to understand that the same variable with the name "cMNum", for example.
In Case of Problems
Please use the following methods in the following order for solving your issues:
- Check the current lab's additional materials.
- Re-read the lab manual to make sure you did not miss anything.
- Google your problems
- Ask the lab assistants for help.
NOTE: In case you find a problem with the documentation, please tell the assitants. Then we can fix the problem and everyone will be happy :)
Lab Tasks
Lab Tutorials
Here you can find lab manuals for the tutorials:
- Lab 1: Kernel Driver
- Lab 2: Building custom SoC on ZedBoard
- Lab 3: Custom IP creation
- Lab 4: Setup 1 board system for the lab
Labs additional readings
Additional reading and more information about the labs can be found here:
General documents
Lab specific documents
Using Own Computer for the Labs
If you plan to use your own computer, please refer to the Using Own Computer page.
Tutorial Labs Archive
Audio Mixer Project
Project Description
Design project is defined in each round for System on Chip design(IAY0550) students with the aim of providing them with real world experience of working on a SoC project, teamwork and project management. This wiki will serve as a platform for students to pass-on their designs and documents to students in the next round of course. Full description of the project can be found on the Project Description page
- Project Description page.
Git
The project code should be stored in git. Every component of the project should be uploaded as a separate branch.
There exists a dedicated Github repository for the course, that can be accessed here: [1]
Team Organization
The following page is for clear and transparent team organization for design project:
