I am currently a research assistant in Tallinn University of Technology (TALTECH)
Major: Hardware Engineering
Thesis Title: Designing a high frequency Phase-Frequency Detector (PFD) using XOR gates and H-Spice simulation
Major: Computer Systems Architecture
Thesis Title: An Efficient FPGA-based Emulation Approach for Fault Simulation of Digital Circuits
Major: Hardware Security
Thesis Title: On the Use of Defensive Schemes for Hardware Security
In this project, I developed a methodology to add online checkers to digital designs at the physical synthesis stage to protect against fabrication-time attacks. I created a suite of tools fully compatible within Cadence Innovus. These tools analyze the placement report from Innovus to identify free gaps around each instance requiring protection, perform ranking analysis based on the Cone of Input (COI) size of the instances, and generate several layouts. Subsequently, another tool evaluates these layouts through an ECO flow, deciding whether to use or discard them based on the overheads imposed on the original layout
My role in the project involved designing various types of hardware Trojans and creating a fully automated flow for Trojan insertion into the submitted layouts by participants, utilizing the ECO features of Innovus. Additionally, I wrote multiple TCL scripts to evaluate the security and PPA metrics of the submissions. To facilitate the use of the target PDK (ASAP7), I customized the libraries and LEF files to ensure compatibility with different versions of Cadence Innovus. A complete flow for the implementation of a sample SHA256 benchmark from RTL to GDS using the ASAP7 PDK is available in our GitHub repository.
For this project, I utilized various techniques during the physical synthesis step to protect the layout, resulting in a secure 65nm CMOS chip. Leveraging Innovus, I implemented advanced methods to modify default attributes of placement, Clock Tree Synthesis (CTS), routing, via insertion, and buffering. Additionally, I designed the PCB and testing environment to verify the fabricated chips. Some of the scripts used in SALSy are publicly available through our GitHub repository.
HeLLoCTF’22 was a global hardware security contest sponsored by Intel, where our team ‘UKU’ from TalTech secured first place. My role in this project involved reverse engineering the state space obfuscation problem to find the correct combination of keys in the designs. The techniques I employed for reverse engineering included using TestMax for ATPG generation and fault injection, JasperGold for formal verification, and various open-source tools like NETA. Additionally, I utilized the simulation tool ModelSim to observe changes in internal values after applying our techniques
In this project, I selected the assertions of more than 100 IPs of OpenTitan SoC, modified the RTL code, and turned them into a synthesizable format. I then synthesized the modified RTL code using Cadence Genus to obtain detailed Power, Performance, and Area (PPA) results. Finally, I performed a taint analysis on the synthesized netlist with Cadence JasperGold SPV to evaluate the security efficiency of each assertion.
In this project, a Xilinx KC705 evaluation board (Kintex 7 FPGA) used to process data in parallel fashion instead of conventional serial-based CPUs in order to accelerate the specified fault injection approach. To achieve the most efficient performance, several tools were developed using C# programming language responsible for preparing and managing the input data and connecting to Xilinx commercial tools.
In this project, a Parallella Desktop 1601 board (with Zynq 7010 SoC) used to take some of the fault injection steps from host computer. The Epiphany III microprocessor available on the board was responsible to act as the manager of the fault injection process, reading data from the SD card and sending the input vectors directly to the FPGA for further processes.
In this project, two Xilinx Spartan6 FPGAs were used; one for implementing preferred units of LEON2 processor, and the other one for generating random input vectors needed for injecting faults to the processor. Xilinx cores were used to handle the timing and connections between FPGAs and host computer. Also, several tools were developed in C# programming language to automate the process of Bit-file generation.
In this project, the transistor level description of the circuit was designed in a way that enabled a PFD to work in a range of Giga Hertz. Suggested modifications to the circuit were designed and verified by HSpice simulation tools.
Awarded the ICT sector’s highest recognition in the field of doctoral studies and a 5,000-euro scholarship. Link to the news
Won the 3rd place in ISPD 2022 Contest: Security Closure of Physical Layouts
Ranked 1st among the same entrance M.Sc. students of Computer Engineering Department in a three-year period of 2015 to 2018
Introduced as a talented student by the Talented Students Guidance Office of Shahid Bahonar University of Kerman
371th place in Computer Engineering Higher Education (M.Sc.) National Universities Entrance Exam among Iranian undergraduate students (nearly 40000 students)
Here, you can find some information about what we are goning to do
Ask me :)