Hello! I am

Mohammad Eslami

I'm a

About

About Me

I am currently a research assistant in Tallinn University of Technology (TALTECH)

  • Name: Mohammad Eslami
  • Address: Akadeemia tee 15a, 12618, Tallinn, Estonia
  • Email: mohammad.eslami@TalTech.ee
Colorlib Template
Colorlib Template
Colorlib Template
Colorlib Template

Education

2010-2014

Bachelor of Computer Engineering

Birjand University, Birjand, Iran

Major: Hardware Engineering
Thesis Title: Designing a high frequency Phase-Frequency Detector (PFD) using XOR gates and H-Spice simulation

2015-2018

M.S. in Computer Engineering

Shahid Bahonar University of Kerman, Kerman, Iran

Major: Computer Systems Architecture
Thesis Title: An Efficient FPGA-based Emulation Approach for Fault Simulation of Digital Circuits

Experience

2015-2018

Acceleration of fault injection techniques using hardware accelerators

RESD lab. SBUK

In this project, a Xilinx KC705 evaluation board (Kintex 7 FPGA) used to process data in parallel fashion instead of conventional serial-based CPUs in order to accelerate the specified fault injection approach. To achieve the most efficient performance, several tools were developed using C# programming language responsible for preparing and managing the input data and connecting to Xilinx commercial tools.

2015-2018

Enhancing runtime of fault injection campaigns by reducing the connections between the host computer and FPGA

RESD lab. SBUK

In this project, a Parallella Desktop 1601 board (with Zynq 7010 SoC) used to take some of the fault injection steps from host computer. The Epiphany III microprocessor available on the board was responsible to act as the manager of the fault injection process, reading data from the SD card and sending the input vectors directly to the FPGA for further processes.

2015-2018

Fault study on LEON2 processor

RESD lab. SBUK

In this project, two Xilinx Spartan6 FPGAs were used; one for implementing preferred units of LEON2 processor, and the other one for generating random input vectors needed for injecting faults to the processor. Xilinx cores were used to handle the timing and connections between FPGAs and host computer. Also, several tools were developed in C# programming language to automate the process of Bit-file generation.

2013-2014

Designing a high frequency Phase-Frequency Detector (PFD) using XOR gates and H-Spice simulation

BEE Research Group

In this project, the transistor level description of the circuit was designed in a way that enabled a PFD to work in a range of Giga Hertz. Suggested modifications to the circuit were designed and verified by HSpice simulation tools.

RESEARCH INTERESTS

Secure Hardware Design

90%

Fault Tolerant Systems Design

80%

Robust and Reliable IC Design

75%

C#

90%

C++

85%

VHDL

80%

Verilog

70%

Matlab

65%

FPGA

60%

Awards

2023

HeLLo: CTF 2022

1st Place

Won the 1st place in HeLLO CTF 2022 Contest

2022

ISPD 2022 Security Contest

3rd Place

Won the 3rd place in ISPD 2022 Contest: Security Closure of Physical Layouts

2015-2018

Top Student

SBUK

Ranked 1st among the same entrance M.Sc. students of Computer Engineering Department in a three-year period of 2015 to 2018

2016-2018

Talented Student Award

SBUK

Introduced as a talented student by the Talented Students Guidance Office of Shahid Bahonar University of Kerman

2015

Top 400 ranked student

National Universities Entrance Exam

371th place in Computer Engineering Higher Education (M.Sc.) National Universities Entrance Exam among Iranian undergraduate students (nearly 40000 students)

Our Projects

Our Projects

Here, you can find some information about what we are goning to do

On the Use of Hardware Monitoring Schemes for Security

This particular position is for a Ph.D. topic related to online monitoring, i.e., on how to best make use of checkers, loggers, instruction traces, etc. for detecting and mitigating security threats. Many of these instruments are already utilized today to increase the reliability of integrated circuits but are less often used to increase the security of said circuits. On one hand, the concern in reliability is to overcome faults. Meanwhile, security concerns are very different: there is an attacker involved in the threat and his malicious goals might include corrupting the computation taking place or leaking confidential information. Modeling the capabilities of the attacker such that successful monitoring schemes can be devised is at the heart of this project. There are also intricate trade-offs to be explored: it is trivial to devise a checker that duplicates the logic and operates both copies in a lockstep fashion. However, the overhead, in this case, is 2x area and 2x power. Insightful checking schemes should aim for much more modest overheads while not compromising detection success.

EITSA18019

This project seeks to establish a professorship and an associated research group in the field of Hardware Security. The research group, named the Centre for Hardware Security, conducts research in all applied aspects of Hardware Security. Our aim is to validate security techniques in real silicon. The Centre's research on integrated circuit (IC) design, electronic design automation (EDA), and cryptographic hardware enables trustworthy IC-based systems to be built. Threats such as Hardware Trojans, reverse engineering, circuit (de)obfuscation, IP piracy, IC overbuilding, side-channel attacks, etc., are addressed through an array of technical countermeasures.

MOBERC35

The fabrication of advanced integrated circuits is often offshored to specialized companies called silicon foundries. Inherently, these companies are not trustworthy. A myriad of problems arises from the lack of trust: piracy, malicious circuit modification, IP infringement, etc. Novel and competent solutions are therefore required to make use of otherwise untrusted silicon – this is the core idea of this action. We propose that a special form of obfuscation, coined merging synthesis, can be employed to effectively confuse an attacker. The concept is to bind together two otherwise unrelated pieces of logic ("merge"), named target and decoy. An attacker then proceeds to mount an attack on the merged logic. It is likely that the attacker will be discouraged to mount said attack since he cannot make sense of the logic. An attacker might also proceed with the attack but promote malicious modifications that only affect the decoy circuitry, thus being transparent to the target circuit.

Contact

Contact Me

Website

m-eslami.ir