Pico CPU: Synthesis


Lab objectives


In this lab we synthesise the CPU on FPGA and write a memory mapped I/O in VHDL and write a calculator with it.



Lab Tasks

  • download the CPU code form here!.
  • download the top level entity from here!
  • download the debouncer for clock debouncing from here!
  • download the seven segment decoder from here!
  • synthesise the design on Nexys 3 board in Xilinx ISE using UCF file from here! here is a guide for ISE.
  • download your design on the board using this guide.
  • check if everything works together. you should be able to see the contents of ACC on the seven segment display.
  • now you need to write a memory mapped I/O controller that reads the switches of your board!
  • write a program that gets commands(add, subtract, and, or,) from 4 most significant switches and data from 4 least significant switches
  • build a calculator using these commands.
  • submit your report!