Before we start (only on the first time use of the tool)

Create some directory for the work with Synopsys (for example hdl) and go into this directory:

1. mkdir hdl
2. cd hdl

1. wget http://ati.ttu.ee/IAY0340/labs/general/Design_Vision_Guide_Files/.synopsys_dc.setup

1. mkdir WORK.syn

Work with Synopsys Design Vision

1. cd hdl

1. cad
2. 3

1. design_vision &

On Figure 1 is the Synopsys main window.

Figure 1. Synopsys Design Vision main window.

Synopsys converts the instructions in the dialog box into a sequence of "shell" commands. You can see the command in the Command Window (by default it is opened in the bottom of the program window). To open a Command Window:

1. Select View->Toolbars->Console

The basic steps for synthesize

1. Select a target technology for synthesis (this is written in the setup file, usually default is okay).
2. Read the HDL design.
3. Synthesize the design (optimizing the logic and mapping to the target technology).
4. Writing out the synthesized netlist in a format, which can be used by gate-level simulation and/or FPGA layout tools.

Reading the input design

Execute the following steps to read in your design:

1. Select File->Analyze
2. In the file browser select the file you wish to synthesize. For example up_down_counter_orig.vhd. All the files must be analyzed in depending sequence (the top of the design hierarchy is the last one).
3. Choose the correct format of the file you want to synthesize and press OK.

If the reading caused an error!!!

There's a possibility that when reading the file an error occurs and Design Vision program closes itself. In this case do the following.

1. Open Design Vision in the directory where the design files are.
2. In the Design Vision command line write analyze -format vhdl filename.vhd, where filename.vhd is the designs filename.
3. If everything went smoothly continues with elaborate step (you can use the File->Elaborate from now on).

Figure 2. Analyze Designs window.

1. Afterwards you need to join all your modules.
   1. Select File->Elaborate
2. From the library select either DEFAULT or WORK. You should select the top module of the hierarchy. For example UP_DOWN_COUNTER(RTL).
3. You need to specify the parameters of your design. If you have generics in your entity description. For example bitwidth = 4
4. Press OK. The Elaborate Designs window is on Figure 3.

Figure 3. Elaborate Designs window.

Navigation in the hierarchy

1. Click on the icon Create Symbol View and you'll see schematic of your design. The same action can be done through Schematic->New Symbol View.
2. Click on the Create Design Schematic to see the netlist.

Figure 4. Symbol view.

Synthesizing the design

Clock signal binding

1. Bind the clock signal with certain frequency. Use the left click to select the port corresponding to the clock signal (on the schematic view of the design).
2. Select Attribute->Specify Clock.
3. Write the clock signal name and specify the period of the clock signal. For example 20 ns.
4. Also specify the time of rising and falling edges of the signal. For example 0 ns and 10 ns.
5. Click OK.

Figure 5. Specify Clock window.

Compiling the design

1. Design->Compile Design.
2. Select Map Effort->Medium.
3. Press OK.

On the Figure 6 is the Compile window view.

Figure 6. Compile window.

Netlist view

Now look at the netlist view.

Generating reports

In order to see the results of the analysis select Design. In the part of the Report select Report Area.... For timing analysis, select Timing->Report Timing Path.... You can also make a combined report with the help of a command report_qor (Figure 7).

Figure 7. Report.

Finally analize the results. To exit the tool go File->Exit.