Test Lab (Optional)

In this lab you are requried to try refreshing your memory about VHDL language and Modelsim simulator. To get familiar with the environment VHDL files mux.vhd and mux_tb.vhd are prepared for you.
Mux.vhd file is the design file of a multiplexer, which its behavior is presented in Table 1. If the control signal CONT_SIG is '1' , then the input A_IN is propagated to the output OUT_SIG, otherwise, if the CONT_SIG is '0' , then input B_IN is propagated to the output.

Table 1: Behaviour of Mux.vhd
CONT_SIG value OUT_SIG value
1 A_IN
0 B_IN
The schematic of multiplexer is on Figure 1.



Simulation Example

Figure 1. Multiplexer diagram

Also testbench for the multiplexer is available in the mux_tb.vhd. The idea of the testbench is to test the behavioral design in simulation by forcing input signals and observe output values. A visualization of simulation example for the multiplexer is illustrated in Figure 2.


Simulation Example
Figure 2. Simulation example

Tasks


  1. Take the guide for ModelSim simulator and try to compile first design file mux.vhd. Also take the testbench file mux_tb.vhd. Simulate the design and check the behavior.

  2. Design mux.vhd contains errors. Fix the errors and make sure that the behavior of the design is correct.

  3. Repeat the simulations using: Xilinx ISE guide.

  4. Change the code so that instead of sensitivity list the process uses wait command. Make sure the code is correct by simulation. Choose a simulator you like best (ISE or ModelSim).

  5. Answer the questions.

Questions


  1. Explain the errors.

  2. What is the difference of entity and architecture?

  3. Can one entity have more than one architecture? Explain.

  4. Is it possible to get right waveforms of the signals during the simulation, even when your design contains behavioral errors? Give an example based on the lab.