Introduction to FSM

1. Consider the following state machine shown in Figure 1. This is a meelay state machine takes one input and looks for a pattern 0110. When ever the pattern is found it gives an output 1.



Table1: State Transition Table

Input	Current State	Next State
0	S0	---
1	S0	---
0	S1	---
1	S1	---
0	S2	---
1	S2	---
0	S3	---
1	S3	---

Table 2: Output Function Table

Input	Current State	Output
0	S0	---
0	S1	---
0	S2	---
0	S3	---
1	S0	---
1	S1	---
1	S2	---
1	S3	---


Fig.1: Example Finite State Machine
2. Make a table next state logic table
3. Similarly, make a table output logic table.
4. Design a VHDL entity with Inputs and outputs as shown in Table 3, as shown in figure below:



Table 3: Top Entity Ports

Name	Port	type
clk	in	STD_LOGIC
inp	in	STD_LOGIC
outp	out	STD_LOGIC




Fig.2:: Mealy machine



5. Design an architecture with following three process blocks
1. next state logic decoder based on table 1
2. two bit state register to store states from s0 to s3
3. output logic decoder based on table 2
6. write a test bench which provides a test pattern of 0,1,1,0,1,1,0,0,1,1,0,1,1,1,1,1
7. Draw a Moore state Machine for the same purpose as shown in the figure below. and describe how it may differ from the current design.



Fig.3:: Moore machine