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Exams

Timeslots for exams

Timeslots for re-exams

Up to 8 students per day. Registration is web-based in OIS. .

Because the exam is oral, the following approximate times should be kept - at 10:00 (15:00) the first four will start. After that, starting approximately from 10:30 (15:30), one student may enter after every 10-20 minutes. The frequency will depend how many are there already in the room. The registration list may be used to define in which order the students enter (but it is optional).

Please be aware that special condition apply when you want to make the exam more than once. Please register only for one day. Those who have registered for many times, only the first one will be kept.
Exceptions, including late arrival, are allowed and it is possible to correct your result but all these things must be agreed beforehand.

Timeslots for office hours

Questions / Topics

Please note the topics are preliminary...

1. VHDL

  1. Description styles - behavioral/functional, structural and data-flow. Main data types, data objects and pre-defined operators.
  2. Main constructs - entity and architecture; their binding. Ports, their declarations and binding.
  3. Additional constructs - subroutines, packages and libraries; their usage.
  4. Processes, activating and suspending them.
  5. Signal assignments, drivers and delays. Differences fro variables. Resolved signals.
  6. Sequential constructs/commands, assertions, procedures.
  7. Parallel constructs/commands (concurrent signal assignments, processes, statements and assertions).
  8. Generating regular structures, generic parameters, configurations.

2. The other hardware description languages

  1. Hardware description languages - motivations and needs, different system level and hardware description languages.
  2. Simulation of digital systems. Different simulation models (unit, zero and delta delay).
  3. Verilog - behavioral, structural and mixed description styles. Differences from VHDL.
  4. Verilog - data types, simulation model and hierarchy. Differences from VHDL.
  5. SystemC - behavioral, structural and mixed description styles. Differences from VHDL.
  6. SystemC - data types, simulation model and hierarchy. Differences from VHDL.
  7. Co-simulation - hardware/software co-simulation, co-simulation of different languages.
  8. Simulation of continuous systems (SPICE, VHDL-AMS). Co-simulation of digital and analog systems.

3. Synthesis

  1. Design flow of digital systems. Levels of abstraction.
  2. Handling large projects when using hardware description languages. Test-bench design methodology.
  3. Synthesizable hardware description languages (VHDL, Verilog) - motivations and needs, limitations, sub-sets, etc.
  4. Physical, logic and register-transfer level syntheses.
  5. High-level synthesis, sub-tasks and methodology.
  6. Scheduling in high-level synthesis.
  7. Assignment and binding in high-level synthesis.
  8. Code transformations at system and algorithmic levels. Effects on hardware and software implementations.

When needed - results of hand-on exercises

Discussing elevator's and processor's architectures and coding styles. Discussing FIR filter's structure. 

Last modified 2015.01.13.