Compendium #1: Adders and Subtractor

Introduction

1. Basic Digital Design Concepts .
   1. How to read a truth table, make boolean equations and make gate level schematic diagrams?

   2. What is registers and latches? How to make a register or a wire with a signal and VHDL?

2. Basic VHDL Concepts.
   1. How to write a simple code for VHDL module? What is an entity? What is an architecture? What is "instantiate" and how do we do it?

   2. How does generate command work? how can it be used for "instantiate"?

3. Synthesis and Target Technologies:

4. What is a critical path? How to calculate critical path of a design? how does critical path affect your systems throughput?

5. What are slices in a FPGA? What are Look-up tables (LUT)?

Basic Digital Design Concepts Problem Set

1. Complete the following truth tables with missing values
   1. AND Gate

      Inputs		Outputs
      In1	In2	Out
      0	0	0
      0	1	X
      1	0	X
      1	1	1

   2. OR Gate

      Inputs		Outputs
      In1	In2	Out
      0	0	0
      0	1	X
      1	0	X
      1	1	1

   3. XOR Gate

      Inputs		Outputs
      In1	In2	Out
      0	0	0
      0	1	X
      1	0	X
      1	1	X

   4. NAND Gate

      Inputs		Outputs
      In1	In2	Out
      0	0	1
      0	1	X
      1	0	X
      1	1	0

   5. NOR Gate

      Inputs		Outputs
      In1	In2	Out
      0	0	1
      0	1	X
      1	0	X
      1	1	0

   6. NOT Gate

      Inputs	Outputs
      In	Out
      0	X
      1	X

   7. Given the following truth table make Karnaugh map (K-Map) of the following design

      Inputs		Outputs
      X	Y	Or	A
      0	0	0	0
      0	1	0	1
      1	0	0	1
      1	1	1	1

   8. Based on the K-Map write the minimized boolean equation

   9. Write the boolean equation for half adder

   10. Write the boolean equation for full adder

   11. Make a schematic diagram for a daisy chain adder using full adders and half adders? Illustrate by making a diagram.

   12. How do we convert a full daisy chain adder into an adder subtracter? Illustrate by making a schematic diagram using full adder and any logical gate necessary.

   13. Illustrate the critical path of a daisy chain adder.

   14. Illustrate the critical path of a daisy chain subtracter.

2. Basic VHDL syntax Problem Set
   1. Considering the following operators write the boolean equation from task 1.h in VHDL syntax. (consider all inputs and outputs as signals) (HINT: LOOK AT THE EXAMPLE)

      VHDL OPERATOR	USE	Example
      AND	logical and infix operator which is used with logical array or boolean type of signals or variables.	in1 and in2
      OR	logical or infix operator which is used with logical array or boolean type of signals or variables.	in1 or in2
      NAND	logical nand infix operator which is used with logical array or boolean type of signals or variables.	in1 nand in2
      NOR	logical nor infix operator which is used with logical array or boolean type of signals or variables.	in1 nor in2
      XOR	logical exclusive or infix operator which is used with logical array or boolean type of signals or variables.	in1 xor in2
      XNOR	logical exclusive nor infix operator which is used with logical array or boolean type of signals or variables.	in1 xnor in2
      NOT	logical or prefix operator which is used with logical array or boolean type of signals or variables.	not in
      <=	Assignment operator which assigns the right hand side signal or variable to the left hand side signals.	out <= in;
      :=	Assignment operator which assigns the right hand side signal or variable to the left hand side variable.	out := in;

   2. If all right hand side is replaced with a signal what changes will take place in the previous equation in 2a? (HINT: READ THE VHDL OPERATOR TABLE in 2a)

   3. If all left hand side is replaced with a signal what changes will take place in the previous equation in 2a? (HINT: READ THE VHDL OPERATOR TABLE in 2a)

   4. Consider a four bit signal s . Write the syntax for instantiation of following entity with signal s using a generate statement according to the following figure.
      entity my_not_gate is
      port (
      input : in std_logic;
      output : out std_logic
      );
      end my_not_gate;
      
3. What is an FPGA? What are the different parts of a single slice of a FPGA. what is Look up table? what is a configurable logic block?