Digital Systems Modeling and Synthesis

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Abstract

Modeling concepts for digital and analog hardware. Hardware description languages - VHDL, SystemVerilog, SystemC. Description levels in VHDL - behavioral/functional, structural and data-flow levels. Simulation engines of hardware description languages. SystemVerilog and SystemC - description levels and simulation engines. Synthesizable VHDL and SystemVerilog. Phases and methods of digital systems synthesis. Description languages for analog hardware - Spice, VHDL-AMS. Simulation and synthesis using modern design tools.

Annotatsioon - Digitaal- ja analoogriistvara modelleerimise alused. Riistvara kirjelduskeeled - VHDL, SystemVerilog, SystemC. VHDL kirjeldustasemed - käitumuslik-funktsionaalne, struktuurne ja andmevoo tase. Riistvara kirjelduskeelte simulatsiooniskeemid. SystemVerilog ja SystemC - kirjeldustasemed ja simulatsiooniskeem. Sünteesitav VHDL ja SystemVerilog. Digitaalsüsteemide sünteesi etapid ja meetodid. Analoogriistvara kirjelduskeeled - Spice, VHDL-AMS. Simuleerimine ja süntees tänapäevaste disainivahenditega.

Course goals

• To give overview about phases, methods and tools of modern microchips and embedded systems design process;
• to give thorough overview about digital systems modeling;
• to give thorough overview about hardware description languages VHDL, SystemVerilog and SystemC, and about their features;
• to give overview about embedded systems modeling languages;
• to give overview about analog systems modeling using languages SPICE and VHDL-AMS;
• to teach how to use different hardware description languages at various abstraction levels;
• to give overview about synthesis of digital systems at register transfer and logic levels;
• to teach how to use commercial simulation an synthesis tools;
• to obtain pre-requisites for follow-up courses of the study line.

Eesmärgid:
• Anda lühiülevaade kaasaegsete mikroskeemide ja sardsüsteemide projekteerimise käigust, meetoditest ja vahenditest;
• anda põhjalik ülevaade digitaalsüsteemide modelleerimisest;
• anda põhjalik ülevaade riistvara kirjelduskeeltest VHDL, SystemVerilog ja SystemC ning nende iseärasustest;
• anda lühiülevaade sardsüsteemide modelleerimisel kasutatavatest keeltest;
• anda lühiülevaade analoog-süsteemide modelleerimisest kasutades keeli SPICE ja VHDL-AMS;
• õpetada erinevate riistvara kirjelduskeelte kasutamist erinevatel disaini- ja abstraktsioonitasemetel;
• anda ülevaade digitaalsüsteemide sünteesist registersiirete ja loogika tasemel;
• õpetada tööstuslike simuleerimis- ja sünteesivahendite kasutamist;
• omandada eeldused järgnevate erialaainete edukaks läbimiseks.

Study outcomes

• Knowledge about phases, methods and tools of modern microchips and embedded systems design process; how to use various hardware description languages at these phases.
• Knowledge how to create models of digital systems in VHDL, SystemVerilog and SystemC.
• Knowledge how to create models of simpler analog systems in SPICE and VHDL-AMS.
• Knowledge how to use at least one commercial simulation tool and one synthesis tool.

Õpiväljundid:
• Kaasaegsete mikroskeemide ja sardsüsteemide projekteerimise põhietappide tundmine, oskus kasutada erinevaid riistvara kirjelduskeeli neil etappidel.
• Oskus luua digitaalseadmete mudeleid nii VHDL-s, SystemVerilog-s, kui ka SystemC-s.
• Oskus luua lihtsamate analoog-süsteemide mudeleid SPICE-s ja VHDL-AMS-s.
• Oskus kasutada vähemalt üht tööstuslikku simuleerimispaketti ja üht sünteesipaketti.

Prerequisites

To pass the course successfully, one must have basic knowledge about programming, Boolean logic, and state machines. Familiarity with UNIX/Linux environment is a plus for hands-on exercises.

Evaluation

Hands-on exercises - During hands-on exercises, different modeling and synthesis tasks are solved using various tools. The exercises cover the use of various hardware description languages to model digital and analog circuits. The exercises also cover synthesis of digital circuits using different technologies.

Prerequisites for the final exam - Reports of hands-on exercises must be presented and defended before exam.

Exam - On the exam, a student will answer to three questions about all topics of the course - one question about VHDL, another about the other hardware description languages and the third one about synthesis related issues.

Content

1.  Lectures
2.  Hands-on exercises
3.  Exam   (eksam) -- Requirement - lab reports accepted before the examination day.

Curricula

• Computer aided design of digital systems (computers, VLSI-s, ASIC-s, etc.) - motivation, tools, possibilities and lacks.
• Hardware description languages - motivations and needs.
• VHDL - behavioral, data-flow and structural models.
• VHDL - main data types, data objects and pre-defined operators, scope of labels.
• VHDL constructs entity, architecture, subroutines and packages.
• Binding of VHDL constructs via interface and assignment lists.
• Libraries in VHDL. Predefined libraries.
• Signal assignments, drivers and delays. Differences fro variables. Resolved signals.
• Parallel constructs/commands (concurrent signal assignments, processes, statements and assertions).
• Ports in entity and component declarations. Port modes.
• Component instantiation - port binding, matching, etc.
• Generating regular structures, generic parameters.
• Processes statement. Activating and suspending processes.
• Sequential constructs/commands. Behavioral hierarchy.
• Simulation of digital systems. VHDL simulation model.
• Configurations. Handling large projects when using VHDL.
• SystemVerilog - main constructs, data types, description styles.
• SystemVerilog - behavioral, data-flow and structural models.
• SystemVerilog - time and simulation models.
• SystemVerilog - builtin features like primitives, nets, gates, etc.
• Synthesizable VHDL, SystemVerilog - motivations and needs, limitations, sub-sets, examples, etc.
• SystemC - main constructs, data types, description styles.
• SystemC - main differences from VHDL and SystemVerilog.
• SystemC - behavioral, data-flow and structural models.
• SystemC - time and simulation models.
• Expanding SystemC - object oriented features.
• Using different hardware description languages together - co-simulation, PLI, etc.
• Basics of analog systems modeling.
• SPICE and its main features - nets, structure, models.
• Analog and mixed signal extensions of hardware description languages - motivation and problems. VHDL-AMS.
• co-simulation of analog and digital systems.
• Different system level and hardware description languages.

Literature

There are many-many books available and the list below is only a brief overview. In principle, one book about one of the languages is enough - the main differences are in syntax. Except maybe that SystemC has more differences...

In TUT library

NB! These are only some of the books at the library.

• Michael John Sebastian Smith. Application-Specific Integrated Circuits. Addison-Wesley, ptk. 10,11 [1997]
• Dirk Jansen et al. (editors). The electronic design automation handbook. Kluwer Academic Publishers, ptk. 4,10-13 [2003]

• Zainalabedin Navabi. Digital system test and testable design: using HDL models and architectures. Springer [2012]

• K.C. Chang. Digital systems design with VHDL and synthesis: an integrated approach. IEEE Computer Society [1999]
• Ben Cohen. VHDL coding styles and methodologies: [... an in-depth tutorial]. Kluwer [1995]
• Stefan Sjoholm and Lennart Lindh. VHDL for designers. Prentice Hall [1997]
• David Pellerin, Douglas Taylor. VHDL made easy. Prentice Hall [1997]
• Kalle Tammemäe. Riistvara kirjeldamiskeel VHDL: metoodiline materjal. Tallinna Tehnikaülikool [2002]

• Ken Coffman. Real world FPGA design with Verilog. Prentice Hall [2000]
• Donald E. Thomas and Philip R. Moorby. The Verilog hardware description language. Kluwer [1996]

• David C. Black, Jack Donovan. SystemC: From the Ground Up. Springer, [2004]

Additional literature

• K.Tammemäe. Riistvara kirjeldamiskeel VHDL. TTÜ toimetus, 1992.   
• K.Tammemäe. Riistvara simuleerimisvahend - VHDL. Avutustehnika & Andmetöötlus (A&A), 4/1992.
• K.Tammemäe. VLSI kõrgtaseme süntees. A&A, 1/1993.
• K.Tammemäe. VHDL täna ja homme. A&A, 9/1993.
• K.Tammemäe. Kas VHDL on sobiv keel sünteesiks. A&A, 7-8/1995.
• P. Ellervee. Riistvara kirjelduskeel Verilog. A&A, 1/1998.

• П. Н. Бибило (P.N.Bibilo). Основы VHDL языка (Osnovy VHDL jazyka). Солон-Р (Solon-R), 2000, ISBN 5-93455-056-X.

• Stuart Sutherland, Simon Davidmann, Peter Flake and Phil Moorby. SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling. Springer
• James M. Lee. Verilog Quickstart: a practical guide to simulation and synthesis in Verilog. Kluwer

• Thorsten Grötker, Stan Liao, Grant Martin, Stuart Swan. System Design with SystemC. Springer, 2002, ISBN 1-4020-7072-1

Plus newer editions of the same books, of course.

WWW

There exist hundreds of web-pages. Some to start with are below.

• VHDL Analysis and Standardization Group
• comp.lang.vhdl FAQ

• Peter J. Ashenden - The Student's Guide to VHDL & The Designer's Guide to VHDL
• Robert Reese - Course notes on Logic Design Course with VHDL & Course notes on Modeling with VHDL

• SystemVerilog.in
• Project Veripage
• Alternate Verilog FAQ
• Verilog Resources

• SystemC Community

Simulator & synthesizer at home

• ModelSim PE Student Edition (Model Technology) - HDL simulator for students (limited design size but enough for term projects, Internet connection required to get license, only for MS Windows).
• WebPACK (Xilinx) - tools to simulate and synthesize smaller designs (MS Windows & Linux-s).
• GHDL and gtkWave - simulator and waveform viewer (MS Windows, Linux-s, etc., GPL - freeware & open-source).
• Active-VHDL Simulation design environment (30-day trial license).
• Green Mountain's compiler/simulator (free demo version, limited code size).

Last modified 2015.01.13.