Difference between revisions of "Kevad 2011"
| Line 12: | Line 12: | ||
08/03, 13:00 Artur Jutman - test systems/equipment installed at ATI '''(please note time)''' | 08/03, 13:00 Artur Jutman - test systems/equipment installed at ATI '''(please note time)''' | ||
| − | 22/03 DDECS try-out's: Anton Karputkin - Probabilistic equivalence checking with HLDD; | + | 22/03 DDECS try-out's: '''Anton Karputkin''' - Probabilistic equivalence checking with HLDD; |
| − | Dmitri Mihhailov - High-performance Hardware Accelerators for Sorting and Managing Priorities | + | '''Dmitri Mihhailov''' - High-performance Hardware Accelerators for Sorting and Managing Priorities |
| − | 29/03 DDECS try-out's: Mihkel Tagel | + | 29/03 DDECS try-out's: '''Mihkel Tagel''' - Communication Modelling and Synthesis for NoC-based Systems with Real-time Constraints |
05/04 Anton Tsertov - about progress in test/debug path modeling in microprocessor-based systems | 05/04 Anton Tsertov - about progress in test/debug path modeling in microprocessor-based systems | ||
Revision as of 11:04, 9 March 2011
Seminarid toimuvad teisipäeviti, 12:00-14:00
09/02 (Wednesday), 14:00, Samary Baranov, High Level Synthesis of Digital Systems (please note the date and time)
15/02, 13:00 Mati Tombak (Dept. of Informatics) - Floorplans, permutations and SSBDD (please note time)
22/02 Sergei Kostin - about Fault Diagnosis
01/03 Anton Tšepurov - zamiaCAD
08/03, 13:00 Artur Jutman - test systems/equipment installed at ATI (please note time)
22/03 DDECS try-out's: Anton Karputkin - Probabilistic equivalence checking with HLDD; Dmitri Mihhailov - High-performance Hardware Accelerators for Sorting and Managing Priorities
29/03 DDECS try-out's: Mihkel Tagel - Communication Modelling and Synthesis for NoC-based Systems with Real-time Constraints
05/04 Anton Tsertov - about progress in test/debug path modeling in microprocessor-based systems
12/04 Igor Aleksejev - about new architectures and solutions in FPGA-based test application (including on the fly reconfigurability, high-speed and at-speed testing, applications to boards and 3D Systems)
19/04 Jevgeni Aleksejev - Fault Management architecture for multi-core and many-core systems based on new and emerging DFT standards.
In the pipeline: Dmitri Mihhailov, Tatjana Schenova, Mairo Leier, Deniss Nikiforov, ...
