Pico CPU:


Verification and Comparison

During this lab you are going to write your test-bench for picoCPU in SystemVerilog. One simple frame of SystemVerilog test-bench is provided to you (picoCPU_TB). You would have co-simulation of your design in VHDL and test-bench in SystemVerilog. This is very easy process in QuestaSim, the only thing you need to worry about is types’ matchinges.
We would like you to test thoroughly instructions of picoCPU(to download the code visit the following page). Everybody is provided with a set of instructions to verify, where every instruction should be independently verified in depth. Please, read material about assertions, coverage in the following links http://www.asic-world.com/systemverilog/tutorial.html SystemVerilog Assertions and Functional Coverage; https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/, https://www.doulos.com/knowhow/sysverilog/tutorial/constraints/
  1. Take additional signals from picoCPU to ports out for your test-bench (instr, instrAdd)
  2. When instrAdd changes generate new instr according your verification policy
  3. Use randomize() to generate random values for operands
  4. It is better to make a class Instruction (see as example https://www.doulos.com/knowhow/sysverilog/tutorial/constraints/ ), where you have all necessary fields of your instruction and can have tasks inside the class
  5. It is better to use assert for checking expected values or sequences of values
  6. Use coverage to observe how thoroughly you have verified your instruction
  7. Create special cases for your instruction (corner cases: maximum, minimum values; zeros etc.)
Set Commands to verify
1 1 11 15 22 28 35
2 2 9 16 20 26 32
3 3 10 17 21 27 33
4 4 14 18 23 29 34
5 5 13 19 24 31 38
6 6 9 16 25 30 36
7 7 14 15 22 28 37

Additional material


Here you can find a example structure of the possible testbench. You can also use this as an template.