Difference between revisions of "CPUProject"

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CPU project is one of the projects designed in department of computer engineering at TTU as a lab project. The main aims of this project are:
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CPU project is one of the projects designed in department of computer engineering at TTU as a lab project to provide students with some tools for studying CPU architecture.
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* Developing a generic CPU without any fancy feature
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* Writing a compiler for it
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* Compiling GCC for this architecture
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* Booting a light linux on it
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= CPU Design=
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= CPU implementations =
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Currently, there are two different CPU implementations:
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* [[picoCPU]]: a very simple, simulation oriented CPU written in VHDL.
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* A [[More Advanced CPU]]: a synthesizable CPU written in VHDL. It has also some more advanced features compared to the picoCPU, like stack, pipeline, etc.
  
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== Functionality Requirements ==
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= picoAssembler =
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The CPU is supposed to be able to perform the following operations:
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PicoAssembler is a simple, reconfigurable assembler that can be used together with the processors described above
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* Addition/Subtraction
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More info on this can be found on the [[PicoAssembler user manual and syntax reference]] page.
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* Increment/Decrement
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* Arithmetic and Logical Shift
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* Bitwise AND, OR, XOR and NOT
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* Negation
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* Load/Store
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* Unconditional Branch (jump)
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* Branch if zero / Branch if Overflow / Branch if Carry
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* Clear Registers/Flags
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* PUSH / POP
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* NOP/HALT
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== Architecture ==
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===Instruction Format===
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Our CPU's instuction has 8 bit of upcode and one operand that can be as long as 32 bit.
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First 3 bits of OPcode are at the moment reserved.
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== Instruction Set (IS)==
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The following instrcutions designed for the CPU:
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{| class="wikitable"
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|-
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! Instruction !! Register Transfer Language !! OpCode !! DPU Command !! Data To DPU !! MemAddress !!  Next PC
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|-
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| Add_A_B || A <-- A + B                    || Example || 00 000 0000 10 || ----    || ---- || PC_out+1 
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|-
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| Add_A_Mem || A <-- A + Mem[Operand]      || Example || 00 000 0000 00 || ----    || Operand || PC_out+1 
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|-
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| Add_A_Dir || A <-- A + Operand            || Example || 00 000 0000 01 || Operand || ---- || PC_out+1 
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|-
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| Sub_A_B || A <-- A - B                    || Example || 00 000 0001 10 || ----    || ---- || Example 
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|-
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| Sub_A_Mem || A <-- A - Mem[Operand]      || Example || 00 000 0001 00 || ----    || Operand || PC_out+1 
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|-
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| Sub_A_Dir || A <-- A - Operand            || Example || 00 000 0001 01 || Operand || ---- || PC_out+1 
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|-
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| IncA || A <-- A + 1                      || Example || 00 000 0000 11 || ----    || ---- || PC_out+1 
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|-
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| DecA || A <-- A - 1                      || Example || 00 000 0001 11 || ----    || ---- || PC_out+1
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|-
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| And_A_B || A <-- A and B                  || Example || 00 000 0100 10 || ----    || ---- || PC_out+1 
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|-
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| OR_A_B || A <-- A or B                    || Example || 00 000 0101 10 || ----    || ---- || PC_out+1 
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|-
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| XOR_A_B || A <-- A xor B                  || Example || 00 000 0110 10 || ----    || ---- || PC_out+1 
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|-
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| FlipA || A <-- not (A)                    || Example || 00 000 1100 00 || ----    || ---- || PC_out+1 
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|-
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| NegA || A <-- not(A) + 1                  || Example || Example || ---- || ---- || PC_out+1 
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|-
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| Jmp || PC <-- Operand                    || Example || Example || ---- || ---- || Depends 
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|-
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| JmpZ || if Z = 1: PC <-- Operand || Example || Example || ---- || ---- || Depends 
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|-
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| JmpOV || if OV = 1: PC <-- Operand || Example || Example || ---- || ---- || Depends 
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|-
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| Jmp_rel || PC <-- PC + Operand  || Example || Example || ---- || ---- ||  Depends 
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|-
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| JMPEQ || if EQ = 1: PC <-- Operand || Example || Example || ---- || ---- || Depends 
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|-
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| ClearZ || Z <--- 0 || Example || Example || ---- || ---- ||  PC_out+1 
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|-
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| ClearOV || OV <--- 0 || Example || Example || ---- || ---- || PC_out+1   
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|-
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| LoadPC  || PC <---- A || Example || Example || ---- || ---- || A 
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|-
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| SavePC || A <---- PC || Example || Example || PC || ---- || PC_out+1   
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|-
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| ShiftArithR || A <-- A(7) & A(7 downto 1)  || Example || Example || ---- || ---- || PC_out+1   
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|-
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| ShiftArithL || A <-- A(7) & A(5 downto 0)& '0' || Example || Example || ---- || ---- || PC_out+1   
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|-
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| ShiftA_R || A <-- A(6 downto 0)& '0' || Example || Example || ---- || ---- || PC_out+1   
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|-
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| ShiftA_L || A <-- '0' & A(7 downto 1)  || Example || Example || ---- || ---- || PC_out+1   
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|-
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| Load_A_Mem || A <-- Mem[Operand] || Example || Example || ---- || Operand || PC_out+1   
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|-
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| Store_A_Mem || Mem[Operand] <-- A || Example || 00 000 0010 -- || ---- || Operand || PC_out+1   
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|-
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| Load_B_Dir || B <-- Operand || Example || 00 000 0010 -- || Operand || ---- || PC_out+1   
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|-
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| Load_B_Mem || B <-- Mem[Operand] || Example || 00 000 0010 -- || ---- || Operand || PC_out+1   
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|-
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| JmpC || if C = 1: PC <-- Operand || Example || 00 000 0010 -- || ---- || ---- || Depends 
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|-
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| ClearC || C <--- 0 || Example || 00 000 0010 -- || ---- || ---- || PC_out+1   
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|-
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| ClearACC || ACC <-- 0 || Example || Example || ---- || ---- || PC_out+1   
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|-
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| RRC || A <-- C & A(7 downto 1) ,C<--  A(0)  || Example || Example || ---- || ---- || PC_out+1   
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|-
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| RLC || A <-- A(6 downto 0) & C ,C<--  A(7) || Example || Example || ---- || ---- || PC_out+1 
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|-
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| PUSH || Mem [0 + SP] <--- A,SP <--- SP + 1 || Example || 00 000 0010 -- || ---- || SP || PC_out+1 
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|-
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| POP || A <--- Mem [0 + SP - 1],SP <--- SP - 1 || Example || Example || ---- || SP - 1 || PC_out+1 
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|-
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| NOP || NOP || Example || 00 000 0010 -- || ---- || ---- || PC_out+1 
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|-
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| HALT || HALT || Example || 00 000 0010 -- || ---- || ---- || PC 
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|}
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===Other instructions implementation===
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the follwoing instructions can be also implemented with the ones in IS:
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* Call "function_name":
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PUSH
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SavePC
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Push
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Jmp "function address"
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POP 
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* Return:
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POP
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Add_A_Dir 4
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LoadPC
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== DataPath unit==
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===Flags===
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== Control unit==
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== Instruction Memory (ROM) ==
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== Data Memory ==
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== Functional Testing ==
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= Assembler =
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= Compiler =
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Latest revision as of 15:32, 24 November 2015

CPU project is one of the projects designed in department of computer engineering at TTU as a lab project to provide students with some tools for studying CPU architecture.

CPU implementations

Currently, there are two different CPU implementations:

  • picoCPU: a very simple, simulation oriented CPU written in VHDL.
  • A More Advanced CPU: a synthesizable CPU written in VHDL. It has also some more advanced features compared to the picoCPU, like stack, pipeline, etc.

picoAssembler

PicoAssembler is a simple, reconfigurable assembler that can be used together with the processors described above More info on this can be found on the PicoAssembler user manual and syntax reference page.

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